In this chapter, a framework is developed for comparison of different post-CMOS interconnect technologies using physical models of transport mechanisms for these novel interconnects. In the first part of the chapter, an overview of CMOS interconnects is provided with an emphasis on the impact of scaling on the performance and energy dissipation of local (<100 gate pitches) interconnects. The second part of the chapter deals with the delay modeling of novel interconnects. The upper bound on the performance of novel interconnects is benchmarked against their conventional CMOS counterparts. A set of guidelines is derived at the device and circuit level for post-CMOS technologies.
|Original language||English (US)|
|Title of host publication||Graphene Nanoelectronics|
|Subtitle of host publication||From Materials to Circuits|
|Number of pages||24|
|ISBN (Print)||1461405475, 9781461405474|
|State||Published - Nov 1 2013|
ASJC Scopus subject areas