Tradeoffs in Buffering Speculative Memory State for Thread-Level Speculation in Multiprocessors

María Jesís Garzarán, Josep Torrellas, Milos Prvulovic, José Maria Llaberia, Victor Viñals Douillet, Lawrence Rauchwerger

Research output: Contribution to journalArticle

Abstract

Thread-Level Speculation (TLS) provides architectural support to aggressively run hard-to-analyze code in parallel. As speculative tasks run concurrently, they generate unsafe or speculative memory state that needs to be separately buffered and managed in the presence of distributed caches and buffers. Such a state may contain multiple versions of the same variable. In this paper, we introduce a novel taxonomy of approaches to buffer and manage multiversion speculative memory state in multiprocessors. We also present a detailed complexity-benefit tradeoff analysis of the different approaches. Finally, we use numerical applications to evaluate the performance of the approaches under a single architectural framework. Our key insights are that support for buffering the state of multiple speculative tasks and versions per processor is more complexity-effective than support for lazily merging the state of tasks with main memory. Moreover, both supports can be gainfully combined and, in large machines, their effect is nearly fully additive. Finally, the more complex support for storing future state in the main memory can boost performance when buffers are under pressure, but hurts performance when squashes are frequent.

Original languageEnglish (US)
Pages (from-to)247-279
Number of pages33
JournalACM Transactions on Architecture and Code Optimization
Volume2
Issue number3
DOIs
StatePublished - Jan 1 2005

Keywords

  • Caching and buffering support
  • Design
  • Performance
  • coherence protocol
  • memory hierarchies
  • shared-memory multiprocessors
  • thread-level speculation

ASJC Scopus subject areas

  • Software
  • Information Systems
  • Hardware and Architecture

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