Tradeoffs in buffering memory state for thread-level speculation in multiprocessors

M. J. Garzaran, M. Prvulovic, J. M. Llaberia, V. Vinals, L. Rauchwerger, J. Torrellas

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Thread-level speculation provides architectural support to aggressively run hard-to-analyze code in parallel. As speculative tasks run concurrently, they generate unsafe or speculative memory state that needs to be separately buffered and managed in the presence of distributed caches and buffers. Such state may contain multiple versions of the same variable. In this paper, we introduce a novel taxonomy of approaches to buffering and managing multi-version speculative memory state in multiprocessors. We also present a detailed complexity-benefit tradeoff analysis of the different approaches. Finally, we use numerical applications to evaluate the performance of the approaches under a single architectural framework. Our key insights are that support for buffering the state of multiple speculative tasks and versions per processor is more complexity-effective than support for merging the state of tasks with main memory lazily. Moreover, both supports can be gainfully combined and, in large machines, their effect is nearly fully additive. Finally, the more complex support for future state in main memory can boost performance when buffers are under pressure, but hurts performance when squashes are frequent.

Original languageEnglish (US)
Title of host publicationProceedings - 9th International Symposium on High-Performance Computer Architecture, HPCA 2003
PublisherIEEE Computer Society
Pages191-202
Number of pages12
ISBN (Electronic)0769518710
DOIs
StatePublished - Jan 1 2003
Externally publishedYes
Event9th IEEE International Symposium on High-Performance Computer Architecture, HPCA 2003 - Anaheim, United States
Duration: Feb 8 2003Feb 12 2003

Publication series

NameProceedings - International Symposium on High-Performance Computer Architecture
Volume12
ISSN (Print)1530-0897

Other

Other9th IEEE International Symposium on High-Performance Computer Architecture, HPCA 2003
CountryUnited States
CityAnaheim
Period2/8/032/12/03

Keywords

  • Memory management
  • Merging
  • Pollution
  • Proposals
  • Taxonomy

ASJC Scopus subject areas

  • Hardware and Architecture

Fingerprint Dive into the research topics of 'Tradeoffs in buffering memory state for thread-level speculation in multiprocessors'. Together they form a unique fingerprint.

  • Cite this

    Garzaran, M. J., Prvulovic, M., Llaberia, J. M., Vinals, V., Rauchwerger, L., & Torrellas, J. (2003). Tradeoffs in buffering memory state for thread-level speculation in multiprocessors. In Proceedings - 9th International Symposium on High-Performance Computer Architecture, HPCA 2003 (pp. 191-202). [1183537] (Proceedings - International Symposium on High-Performance Computer Architecture; Vol. 12). IEEE Computer Society. https://doi.org/10.1109/HPCA.2003.1183537