TY - GEN
T1 - Tradeoffs in buffering memory state for thread-level speculation in multiprocessors
AU - Garzaran, M. J.
AU - Prvulovic, M.
AU - Llaberia, J. M.
AU - Vinals, V.
AU - Rauchwerger, L.
AU - Torrellas, J.
N1 - Funding Information:
This work was supported in part by the National Science Foundation under grants EIA-0081307, EIA-0072102, and EIA-0103741; by DARPA under grant F30602-01-C-0078; by the Ministry of Education of Spain under grant TIC 2001-0995-C02-02; and by gifts fromIBM and Intel.
Publisher Copyright:
© 2003 IEEE.
PY - 2003
Y1 - 2003
N2 - Thread-level speculation provides architectural support to aggressively run hard-to-analyze code in parallel. As speculative tasks run concurrently, they generate unsafe or speculative memory state that needs to be separately buffered and managed in the presence of distributed caches and buffers. Such state may contain multiple versions of the same variable. In this paper, we introduce a novel taxonomy of approaches to buffering and managing multi-version speculative memory state in multiprocessors. We also present a detailed complexity-benefit tradeoff analysis of the different approaches. Finally, we use numerical applications to evaluate the performance of the approaches under a single architectural framework. Our key insights are that support for buffering the state of multiple speculative tasks and versions per processor is more complexity-effective than support for merging the state of tasks with main memory lazily. Moreover, both supports can be gainfully combined and, in large machines, their effect is nearly fully additive. Finally, the more complex support for future state in main memory can boost performance when buffers are under pressure, but hurts performance when squashes are frequent.
AB - Thread-level speculation provides architectural support to aggressively run hard-to-analyze code in parallel. As speculative tasks run concurrently, they generate unsafe or speculative memory state that needs to be separately buffered and managed in the presence of distributed caches and buffers. Such state may contain multiple versions of the same variable. In this paper, we introduce a novel taxonomy of approaches to buffering and managing multi-version speculative memory state in multiprocessors. We also present a detailed complexity-benefit tradeoff analysis of the different approaches. Finally, we use numerical applications to evaluate the performance of the approaches under a single architectural framework. Our key insights are that support for buffering the state of multiple speculative tasks and versions per processor is more complexity-effective than support for merging the state of tasks with main memory lazily. Moreover, both supports can be gainfully combined and, in large machines, their effect is nearly fully additive. Finally, the more complex support for future state in main memory can boost performance when buffers are under pressure, but hurts performance when squashes are frequent.
KW - Memory management
KW - Merging
KW - Pollution
KW - Proposals
KW - Taxonomy
UR - http://www.scopus.com/inward/record.url?scp=43949089615&partnerID=8YFLogxK
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U2 - 10.1109/HPCA.2003.1183537
DO - 10.1109/HPCA.2003.1183537
M3 - Conference contribution
AN - SCOPUS:43949089615
T3 - Proceedings - International Symposium on High-Performance Computer Architecture
SP - 191
EP - 202
BT - Proceedings - 9th International Symposium on High-Performance Computer Architecture, HPCA 2003
PB - IEEE Computer Society
T2 - 9th IEEE International Symposium on High-Performance Computer Architecture, HPCA 2003
Y2 - 8 February 2003 through 12 February 2003
ER -