Tradeoff routing resource, runtime and quality in buffered routing

Xiaoping Tang, Martin D F Wong

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

With the wide use of hard macros and IP blocks in design, buffered routing (simultaneous routing and buffer insertion) becomes unavoidable. Routing resource allocation and distribution are serious concerns in buffered routing of deep submicron design. The capability of capturing the tradeoff between routing resource cost and signal delay is crucial in practice since the resource overuse of min-delay solution may cause congestion problem (congestion also means overinserting buffers). However, many existing algorithms are mainly designed to minimize signal delay. In the paper, we first study the problem of minimizing the linear combination of delay and cost, and extend the graph-based algorithm in [10] to solve it. We then show that a variant of the algorithm can solve other problems such as maximizing delay reduction to cost ratio, minimizing routing cost subject to a delay constraint, and minimizing delay subject to the cost not exceeding a given budget. We also develop a hierarchical approach to buffered routing construction for problems with large number of sinks to tradeoff solution quality and runtime.

Original languageEnglish (US)
Title of host publicationProceedings of the ASP - DAC 2004 Asia and South Pacific Design Automation Conference - 2004
Pages430-433
Number of pages4
StatePublished - 2004
EventProceedings of the ASP - DAC 2004 Asia and South Pacific Design Automation Conference - 2004 - Yokohama, Japan
Duration: Jan 27 2004Jan 30 2004

Other

OtherProceedings of the ASP - DAC 2004 Asia and South Pacific Design Automation Conference - 2004
CountryJapan
CityYokohama
Period1/27/041/30/04

ASJC Scopus subject areas

  • Engineering(all)

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  • Cite this

    Tang, X., & Wong, M. D. F. (2004). Tradeoff routing resource, runtime and quality in buffered routing. In Proceedings of the ASP - DAC 2004 Asia and South Pacific Design Automation Conference - 2004 (pp. 430-433)