Toward the predictable integration of real-time COTS based systems

Rodolfo Pellizzoni, Marco Caccamo

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The integration phase of real-time COTS-based systems is often problematic because when multiple tasks run concurrently, the interference at the bus level between cache fetching activities and I/O peripheral transactions is significant and causes unpredictable behaviors: experimentally, tasks can have computation time variance up to 50%. In this work, we present a theoretical framework able to model the interaction between CPU and peripherals contending for shared main memory through the Front Side Bus (FSB). We first show how to compute worst case execution times for a task given a trace of its cache activity and given an upper bound function that models peripheral activities; then, we introduce the novel idea of "hardware server" as a means of controlling the unpredictable behavior of COTS peripheral components.

Original languageEnglish (US)
Title of host publicationProceedings - 28th IEEE International Real-Time Systems Symposium, RTSS 2007
Pages73-82
Number of pages10
DOIs
StatePublished - Dec 1 2007
Event28th IEEE International Real-Time Systems Symposium, RTSS 2007 - Tucson, AZ, United States
Duration: Dec 3 2007Dec 6 2007

Publication series

NameProceedings - Real-Time Systems Symposium
ISSN (Print)1052-8725

Other

Other28th IEEE International Real-Time Systems Symposium, RTSS 2007
Country/TerritoryUnited States
CityTucson, AZ
Period12/3/0712/6/07

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Computer Networks and Communications

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