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Toward a cost-effective DSM organization that exploits processor-memory integration
Josep Torrellas
, Liuxi Yang
, Anthony Trung Nguyen
Electrical and Computer Engineering
Information Trust Institute
Coordinated Science Lab
Siebel School of Computing and Data Science
Research output
:
Contribution to conference
›
Paper
›
peer-review
Overview
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Keyphrases
Distributed Storage
100%
Memory Organization
100%
Memory Integration
100%
Microprocessor
66%
Caching
66%
Transistor
33%
On chip
33%
Reconfiguration
33%
Computing Node
33%
Shared Memory
33%
Main Memory
33%
Multiprocessor
33%
Shared-memory multiprocessors
33%
Uniprocessor
33%
Cache Coherence Protocol
33%
Cache Coherent
33%
VLSI chip
33%
In-memory
33%
Off-the-shelf Hardware
33%
NuMA
33%
Close-coupling
33%
Commercial Considerations
33%
Computer Science
Control Directory
100%
Shared Memory
100%
Microprocessor Chips
100%
Shared Memory Multiprocessor
50%
Main Memory
50%
multi-processor
50%
Cache Coherence
50%
Shelf Hardware
50%
Computer Hardware
50%