Total leakage optimization strategies for multi-level caches

Gate leakage current is fast becoming a major contributor to total leakage and will become the dominant leakage mechanism as gate oxide is scaled below 10Å. This has special relevance for caches, because they are often the largest component by area in state-of-the-art microprocessors, and leakage is their major contribution to overall chip power. In this paper, we investigate the impact of T_ox and V_th on power performance trade-offs for on-chip caches. We examine the optimization of the various components of a single level cache and then extend this to two level cache systems. In addition to leakage, our studies also account for the dynamic power expended as a result of cache misses. Our results show that, surprisingly, one can often reduce overall power by increasing the size of the L2 cache if we only allow one pair of V_th/T_ox in L2. We further show that two V _th's and two T_ox's are sufficient to get close to an optimal solution and that V_th is generally a better design knob than T_ox for leakage optimization, thus it is better to restrict the number of T_ox's rather than V_th's if cost is a concern. Finally, we show that optimal power performance points are remarkably robust to wide changes in ambient temperature.