Total leakage optimization strategies for multi-level caches

Robert Bai, Nam Sung Kim, Dennis Sylvester, Trevor Mudge

Research output: Contribution to conferencePaperpeer-review

Abstract

Gate leakage current is fast becoming a major contributor to total leakage and will become the dominant leakage mechanism as gate oxide is scaled below 10Å. This has special relevance for caches, because they are often the largest component by area in state-of-the-art microprocessors, and leakage is their major contribution to overall chip power. In this paper, we investigate the impact of Tox and Vth on power performance trade-offs for on-chip caches. We examine the optimization of the various components of a single level cache and then extend this to two level cache systems. In addition to leakage, our studies also account for the dynamic power expended as a result of cache misses. Our results show that, surprisingly, one can often reduce overall power by increasing the size of the L2 cache if we only allow one pair of Vth/Tox in L2. We further show that two V th's and two Tox's are sufficient to get close to an optimal solution and that Vth is generally a better design knob than Tox for leakage optimization, thus it is better to restrict the number of Tox's rather than Vth's if cost is a concern. Finally, we show that optimal power performance points are remarkably robust to wide changes in ambient temperature.

Original languageEnglish (US)
Pages381-384
Number of pages4
DOIs
StatePublished - 2005
Externally publishedYes
Event2005 ACM Great Lakessymposium on VLSI, GLSVLSI'05 - Chicago, IL, United States
Duration: Apr 17 2005Apr 19 2005

Other

Other2005 ACM Great Lakessymposium on VLSI, GLSVLSI'05
CountryUnited States
CityChicago, IL
Period4/17/054/19/05

Keywords

  • Cache memory
  • Gate leakage
  • Low power

ASJC Scopus subject areas

  • Engineering(all)

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