Tolerating cache-miss latency with multipass pipelines

Ronald D. Barnes; Shane Ryoo; Wen Mei W. Hwu

doi:10.1109/MM.2006.25

Tolerating cache-miss latency with multipass pipelines

Ronald D. Barnes, Shane Ryoo, Wen Mei W. Hwu

Research output: Contribution to journal › Article

Abstract

Multipass pipelining uses compile-time scheduling to exploit parallelism and persistent advance execution to achieve memory-latency tolerance, while maintaining the simplicity of an in-order design.

Original language	English (US)
Pages (from-to)	40-47
Number of pages	8
Journal	IEEE Micro
Volume	26
Issue number	1
DOIs	https://doi.org/10.1109/MM.2006.25
State	Published - Jan 1 2006

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ASJC Scopus subject areas

Software
Hardware and Architecture
Electrical and Electronic Engineering

Cite this

Barnes, R. D., Ryoo, S., & Hwu, W. M. W. (2006). Tolerating cache-miss latency with multipass pipelines. IEEE Micro, 26(1), 40-47. https://doi.org/10.1109/MM.2006.25

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Access to Document

10.1109/MM.2006.25