Tolerating cache-miss latency with multipass pipelines

Ronald D. Barnes; Shane Ryoo; Wen Mei W. Hwu

doi:10.1109/MM.2006.25

Tolerating cache-miss latency with multipass pipelines

Ronald D. Barnes, Shane Ryoo, Wen Mei W. Hwu

Research output: Contribution to journal › Article › peer-review

Abstract

Multipass pipelining uses compile-time scheduling to exploit parallelism and persistent advance execution to achieve memory-latency tolerance, while maintaining the simplicity of an in-order design.

Original language	English (US)
Pages (from-to)	40-47
Number of pages	8
Journal	IEEE Micro
Volume	26
Issue number	1
DOIs	https://doi.org/10.1109/MM.2006.25
State	Published - Jan 1 2006

ASJC Scopus subject areas

Software
Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/MM.2006.25

Fingerprint Dive into the research topics of 'Tolerating cache-miss latency with multipass pipelines'. Together they form a unique fingerprint.

Cite this

@article{6614079013eb42d38eba087673352f6b,

title = "Tolerating cache-miss latency with multipass pipelines",

abstract = "Multipass pipelining uses compile-time scheduling to exploit parallelism and persistent advance execution to achieve memory-latency tolerance, while maintaining the simplicity of an in-order design.",

author = "Barnes, {Ronald D.} and Shane Ryoo and Hwu, {Wen Mei W.}",

year = "2006",

month = jan,

day = "1",

doi = "10.1109/MM.2006.25",

language = "English (US)",

volume = "26",

pages = "40--47",

journal = "IEEE Micro",

issn = "0272-1732",

publisher = "IEEE Computer Society",

number = "1",

}

TY - JOUR

T1 - Tolerating cache-miss latency with multipass pipelines

AU - Barnes, Ronald D.

AU - Ryoo, Shane

AU - Hwu, Wen Mei W.

PY - 2006/1/1

Y1 - 2006/1/1

N2 - Multipass pipelining uses compile-time scheduling to exploit parallelism and persistent advance execution to achieve memory-latency tolerance, while maintaining the simplicity of an in-order design.

AB - Multipass pipelining uses compile-time scheduling to exploit parallelism and persistent advance execution to achieve memory-latency tolerance, while maintaining the simplicity of an in-order design.

UR - http://www.scopus.com/inward/record.url?scp=33644913107&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=33644913107&partnerID=8YFLogxK

U2 - 10.1109/MM.2006.25

DO - 10.1109/MM.2006.25

M3 - Article

AN - SCOPUS:33644913107

VL - 26

SP - 40

EP - 47

JO - IEEE Micro

JF - IEEE Micro

SN - 0272-1732

IS - 1

ER -