Tolerating cache-miss latency with multipass pipelines

Ronald D. Barnes, Shane Ryoo, Wen-Mei W Hwu

Research output: Contribution to journalArticle

Abstract

Multipass pipelining uses compile-time scheduling to exploit parallelism and persistent advance execution to achieve memory-latency tolerance, while maintaining the simplicity of an in-order design.

Original languageEnglish (US)
Pages (from-to)40-47
Number of pages8
JournalIEEE Micro
Volume26
Issue number1
DOIs
StatePublished - Jan 1 2006

Fingerprint

Pipelines
Scheduling
Data storage equipment

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Tolerating cache-miss latency with multipass pipelines. / Barnes, Ronald D.; Ryoo, Shane; Hwu, Wen-Mei W.

In: IEEE Micro, Vol. 26, No. 1, 01.01.2006, p. 40-47.

Research output: Contribution to journalArticle

Barnes, Ronald D. ; Ryoo, Shane ; Hwu, Wen-Mei W. / Tolerating cache-miss latency with multipass pipelines. In: IEEE Micro. 2006 ; Vol. 26, No. 1. pp. 40-47.
@article{6614079013eb42d38eba087673352f6b,
title = "Tolerating cache-miss latency with multipass pipelines",
abstract = "Multipass pipelining uses compile-time scheduling to exploit parallelism and persistent advance execution to achieve memory-latency tolerance, while maintaining the simplicity of an in-order design.",
author = "Barnes, {Ronald D.} and Shane Ryoo and Hwu, {Wen-Mei W}",
year = "2006",
month = "1",
day = "1",
doi = "10.1109/MM.2006.25",
language = "English (US)",
volume = "26",
pages = "40--47",
journal = "IEEE Micro",
issn = "0272-1732",
publisher = "IEEE Computer Society",
number = "1",

}

TY - JOUR

T1 - Tolerating cache-miss latency with multipass pipelines

AU - Barnes, Ronald D.

AU - Ryoo, Shane

AU - Hwu, Wen-Mei W

PY - 2006/1/1

Y1 - 2006/1/1

N2 - Multipass pipelining uses compile-time scheduling to exploit parallelism and persistent advance execution to achieve memory-latency tolerance, while maintaining the simplicity of an in-order design.

AB - Multipass pipelining uses compile-time scheduling to exploit parallelism and persistent advance execution to achieve memory-latency tolerance, while maintaining the simplicity of an in-order design.

UR - http://www.scopus.com/inward/record.url?scp=33644913107&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=33644913107&partnerID=8YFLogxK

U2 - 10.1109/MM.2006.25

DO - 10.1109/MM.2006.25

M3 - Article

AN - SCOPUS:33644913107

VL - 26

SP - 40

EP - 47

JO - IEEE Micro

JF - IEEE Micro

SN - 0272-1732

IS - 1

ER -