Tolerating cache-miss latency with multipass pipelines

Ronald D. Barnes, Shane Ryoo, Wen Mei W. Hwu

Research output: Contribution to journalArticle

Abstract

Multipass pipelining uses compile-time scheduling to exploit parallelism and persistent advance execution to achieve memory-latency tolerance, while maintaining the simplicity of an in-order design.

Original languageEnglish (US)
Pages (from-to)40-47
Number of pages8
JournalIEEE Micro
Volume26
Issue number1
DOIs
StatePublished - Jan 1 2006

    Fingerprint

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this