@article{6614079013eb42d38eba087673352f6b,
title = "Tolerating cache-miss latency with multipass pipelines",
abstract = "Multipass pipelining uses compile-time scheduling to exploit parallelism and persistent advance execution to achieve memory-latency tolerance, while maintaining the simplicity of an in-order design.",
author = "Barnes, {Ronald D.} and Shane Ryoo and Hwu, {Wen Mei W.}",
note = "We acknowledge the past and present mem bers of the Illinois Microarchitecture Project utilizing Advanced Compiler Technology (IMPACT) research group for their feedback and assistance. The Gigascale Systems Research Center, US National Science Foundation ITR Grant 86096, and generous gift funds from Intel Corp. partially supported this work.",
year = "2006",
month = jan,
doi = "10.1109/MM.2006.25",
language = "English (US)",
volume = "26",
pages = "40--47",
journal = "IEEE Micro",
issn = "0272-1732",
publisher = "IEEE Computer Society",
number = "1",
}