TLB CONSISTENCY ON HIGHLY-PARALLEL SHARED-MEMORY MULTIPROCESSORS.

Patricia J. Teller, Richard Kenner, Marc Snir

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Multiprocessors that store the same shared data in different caches must ensure that these caches have consistent copies. Almost all known solutions to this cache consistency problem are only suitable for architectures with a few tens of processing elements (PEs). Efficient solutions to the TLB (translation lookaside buffer) consistency problem, a special case of the cache consistency problem, can be found for highly parallel, shared-memory multiprocessors (HPSMMs) with many hundreds of PEs for the following reasons: the number of references to address translation information per modification is very large; the cache for storing translation information can be present anywhere on the path from the PEs to memory; when the memory mapping needs to be modified, one can often select which translation information to change; and obsolete mapping information can be used until permanent changes must be made. Three general methods are presented that use these features and can be used on HIPSMMs to maintain TLB consistency. Some interesting issues inherent to the TLB consistency problem and the support of a demand-paged virtual memory system on a HPSMM are presented.

Original languageEnglish (US)
Title of host publicationProceedings of the Hawaii International Conference on System Science
PublisherIEEE
Pages184-193
Number of pages10
ISBN (Print)0818608412, 9780818608414
DOIs
StatePublished - 1988
Externally publishedYes

Publication series

NameProceedings of the Hawaii International Conference on System Science
ISSN (Print)0073-1129

ASJC Scopus subject areas

  • Computer Science(all)

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