Timing-driven routing for symmetrical array-based FPGAs

Yao Wen Chang, Kai Zhu, D. F. Wong

Research output: Contribution to journalArticle

Abstract

In this paper we present a timing-driven router for symmetrical array-based FPGAs. The routing resources in the FPGAs consist of segments of various lengths. Researchers have shown that the number of segments, instead of wirelength, used by a net is the most critical factor in controlling routing delay in an FPGA. Thus, the traditional measure of routing delay on the basis of geometric distance of a signal is not accurate. To consider wirelength and delay simultaneously, we study a model of timing-driven routing trees, arising from the special properties of FPGA routing architectures. Based on the solutions to the routing-tree problem, we present a routing algorithm that is able to utilize various routing segments with global considerations to meet timing constraints. Experimental results show that our approach is very effective in reducing timing violations.

Original languageEnglish (US)
Pages (from-to)433-450
Number of pages18
JournalACM Transactions on Design Automation of Electronic Systems
Volume5
Issue number3
DOIs
StatePublished - 2000

Keywords

  • Algorithms
  • Computer-aided design of VLSI
  • Design
  • Experimentation
  • Field-programmable gate array
  • Layout
  • Measurement
  • Performance
  • Synthesis

ASJC Scopus subject areas

  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

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