Timing-driven routing for symmetrical-array-based FPGAs

Kai Zhu, Yao Wen Chang, D. F. Wong

Research output: Contribution to conferencePaperpeer-review

Abstract

In this paper, we present a timing-driven global router for symmetrical-array-based FPGAs. The routing resources in the symmetrical-array-based FPGAs consist of segments of various lengths. Researchers have shown that the number of segments, instead of wirelength, used by a net is the most critical factor in controlling routing delay in an FPGA. Thus, traditional measure of routing delay based on the geometric distance of a signal is not accurate. To consider wirelength and delay simultaneously, we study a model of timing-driven routing trees, arising from the special properties of FPGA routing architectures. We explore the complexity of the routing-tree problem and present efficient and effective approximation algorithms for the problem. Based on the solutions to the routing-tree problem, we present a global-routing algorithm which is able to utilize various routing segments with global consideration to meet the timing constraints. Experimental results on benchmark circuits show that our approach is promising.

Original languageEnglish (US)
Pages628-633
Number of pages6
StatePublished - Dec 1 1998
Externally publishedYes
EventProceedings of the 1998 IEEE International Conference on Computer Design - Austin, TX, USA
Duration: Oct 5 1998Oct 7 1998

Other

OtherProceedings of the 1998 IEEE International Conference on Computer Design
CityAustin, TX, USA
Period10/5/9810/7/98

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'Timing-driven routing for symmetrical-array-based FPGAs'. Together they form a unique fingerprint.

Cite this