Timing-constrained and voltage-island-aware voltage assignment

Huaizhi Wu, Martin D F Wong, I. Min Liu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Multi-Vdd is an effective method to reduce both leakage and dynamic power. A key challenge in a multi-Vdd design is to limit the design cost and the demand for level shifters. This can be tackled by grouping cells of different supply voltages into a small number of voltage islands. Recently, an elegant algorithm [7] is proposed for generating voltage islands that balance the power versus design cost tradeoff under performance requirement, according to the placement proximity of the critical cells. One prerequisite of [7] is an initial voltage assignment at the standard cell level that meets timing. In this paper, we present a novel method to produce quality voltage assignment to [7], which not only meets timing but also forms good proximity of the critical cells to provide [7] with a smooth input. The algorithm is based on effective delay budgeting and efficient computation of physical proximity by Voronoi diagram. Our experiments on real industrial designs show that our algorithm leads to 25 - 75% improvement in the voltage island generation, with the computation time only linear to the design size.

Original languageEnglish (US)
Title of host publication2006 43rd ACM/IEEE Design Automation Conference, DAC'06
Pages429-432
Number of pages4
DOIs
StatePublished - Dec 1 2006

Publication series

NameProceedings - Design Automation Conference
ISSN (Print)0738-100X

Keywords

  • Low power
  • Timing
  • Voltage assignment
  • Voronoi diagram

ASJC Scopus subject areas

  • Hardware and Architecture
  • Control and Systems Engineering

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