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Timing analysis for sensor network nodes of the Atmega processor family
Sibin Mohan
, Frank Mueller
, David Whalley
, Christopher Healy
Research output
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Contribution to journal
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Conference article
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peer-review
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Dive into the research topics of 'Timing analysis for sensor network nodes of the Atmega processor family'. Together they form a unique fingerprint.
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Keyphrases
Timing Analysis
100%
Sensor Node
100%
ATmega
100%
Atmel
75%
Lower End
50%
Popular
25%
Analytical Method
25%
Embedded Systems
25%
Control Variables
25%
Model-based Control
25%
Networked Systems
25%
Real-time Constraints
25%
Berkeley
25%
Mote
25%
NesC
25%
Processor Architecture
25%
Sensor Node Architecture
25%
Embedded Processor
25%
Variable Cycle
25%
Tool Support
25%
Cycle-accurate Simulator
25%
Real-time Schedulability Analysis
25%
Static Timing
25%
Control Hazard
25%
Embedded Architecture
25%
Computer Science
Timing Analysis
100%
Sensor Network
100%
Sensor Node
66%
Time Constraint
33%
First Set
33%
Analysis Framework
33%
Schedulability Analysis
33%
Berkeley Mote
33%
Embedded Computer
33%
Embedded Processor
33%
Cycle-Accurate Simulator
33%
Control Hazard
33%
Processor Architecture
33%