TY - GEN
T1 - Time redundant parity for low-cost transient error detection
AU - Palframan, David J.
AU - Kim, Nam Sung
AU - Lipasti, Mikko H.
PY - 2011/5/31
Y1 - 2011/5/31
N2 - With shrinking transistor sizes and supply voltages, errors in combinational logic due to radiation particle strikes are on the rise. A broad range of applications will soon require protection from this type of error, requiring an effective and inexpensive solution. Many previously proposed logic protection techniques rely on duplicate logic or latches, incurring high overheads. In this paper, we present a technique for transient error detection using parity trees for power and area efficiency. This approach is highly customizable, allowing adjustment of a number of parameters for optimal error coverage and overhead. We present simulation results comparing our scheme to latch duplication, showing on average greater than 55% savings in area and power overhead for the same error coverage. We also demonstrate adding protection to reach a target logic soft error rate, constituting at best a 59X reduction in the error rate with under 2% power and area overhead.
AB - With shrinking transistor sizes and supply voltages, errors in combinational logic due to radiation particle strikes are on the rise. A broad range of applications will soon require protection from this type of error, requiring an effective and inexpensive solution. Many previously proposed logic protection techniques rely on duplicate logic or latches, incurring high overheads. In this paper, we present a technique for transient error detection using parity trees for power and area efficiency. This approach is highly customizable, allowing adjustment of a number of parameters for optimal error coverage and overhead. We present simulation results comparing our scheme to latch duplication, showing on average greater than 55% savings in area and power overhead for the same error coverage. We also demonstrate adding protection to reach a target logic soft error rate, constituting at best a 59X reduction in the error rate with under 2% power and area overhead.
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M3 - Conference contribution
AN - SCOPUS:79957540483
SN - 9783981080179
T3 - Proceedings -Design, Automation and Test in Europe, DATE
SP - 52
EP - 57
BT - Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 2011
T2 - 14th Design, Automation and Test in Europe Conference and Exhibition, DATE 2011
Y2 - 14 March 2011 through 18 March 2011
ER -