ThunderGP: HLS-based graph processing framework on fpgas

Xinyu Chen, Hongshi Tan, Yao Chen, Bingsheng He, Weng Fai Wong, Deming Chen

Research output: Chapter in Book/Report/Conference proceedingConference contribution


FPGA has been an emerging computing infrastructure in datacenters benefiting from features of fine-grained parallelism, energy efficiency, and reconfigurability. Meanwhile, graph processing has attracted tremendous interest in data analytics, and its performance is in increasing demand with the rapid growth of data. Many works have been proposed to tackle the challenges of designing efficient FPGA-based accelerators for graph processing. However, the largely overlooked programmability still requires hardware design expertise and sizable development efforts from developers. In order to close the gap, we propose ThunderGP, an open-source HLS-based graph processing framework on FPGAs, with which developers could enjoy the performance of FPGA-accelerated graph processing by writing only a few high-level functions with no knowledge of the hardware. ThunderGP adopts the Gather-Apply-Scatter (GAS) model as the abstraction of various graph algorithms and realizes the model by a build-in highly-paralleled and memory-efficient accelerator template. With high-level functions as inputs, ThunderGP automatically explores the massive resources and memory bandwidth of multiple Super Logic Regions (SLRs) on FPGAs to generate accelerator and then deploys the accelerator and schedules tasks for the accelerator. We evaluate ThunderGP with seven common graph applications. The results show that accelerators on real hardware platforms deliver 2.9 times speedup over the state-of-the-art approach, running at 250MHz and achieving throughput up to 6,400 MTEPS (Million Traversed Edges Per Second). We also conduct a case study with ThunderGP, which delivers up to 419 times speedup over the CPU-based design and requires significantly reduced development efforts. This work is open-sourced on Github at

Original languageEnglish (US)
Title of host publicationFPGA 2021 - 2021 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays
PublisherAssociation for Computing Machinery
Number of pages12
ISBN (Electronic)9781450382182
StatePublished - Feb 17 2021
Event2021 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA 2021 - Virtual, Online, United States
Duration: Feb 28 2021Mar 2 2021

Publication series

NameFPGA 2021 - 2021 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays


Conference2021 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA 2021
Country/TerritoryUnited States
CityVirtual, Online


  • Fpga
  • Framework
  • Graph processing
  • High-level synthesis
  • Multiple super logic regions

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering


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