Abstract
To effectively exploit instruction level parallelism, the compiler must move instructions across branches. When an instruction is moved above a branch that it is control dependent on, it is considered to be speculatively executed since it is executed before it is known whether or not its result is needed. There are potential hazards when speculatively executing instructions. If these hazards can be eliminated, the compiler can more aggressively schedule the code. The hazards of speculative execution are outlined in this paper. Three architectural models: restricted, general, and boosting, which have increasing amounts of support for removing these hazards are discussed. The performance gained by each level of additional hardware support is analyzed using the IMPACT C compiler which performs superblock scheduling for superscalar and superpipelined processors.
| Original language | English (US) |
|---|---|
| Pages (from-to) | 481-494 |
| Number of pages | 14 |
| Journal | IEEE Transactions on Computers |
| Volume | 44 |
| Issue number | 4 |
| DOIs | |
| State | Published - Apr 1995 |
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Keywords
- Conditional branches
- exception handling
- speculative execution
- static code scheduling
- superblock
- superpipelining
- superscalar
ASJC Scopus subject areas
- Software
- Theoretical Computer Science
- Hardware and Architecture
- Computational Theory and Mathematics
Cite this
Three Architectural Models for Compiler-Controlled Speculative Execution. / Chang, Pohua P.; Warter, Nancy J.; Mahlke, Scott A.; Chen, William Y.; Hwu, Wen Mei W.
In: IEEE Transactions on Computers, Vol. 44, No. 4, 04.1995, p. 481-494.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - Three Architectural Models for Compiler-Controlled Speculative Execution
AU - Chang, Pohua P.
AU - Warter, Nancy J.
AU - Mahlke, Scott A.
AU - Chen, William Y.
AU - Hwu, Wen Mei W.
PY - 1995/4
Y1 - 1995/4
N2 - To effectively exploit instruction level parallelism, the compiler must move instructions across branches. When an instruction is moved above a branch that it is control dependent on, it is considered to be speculatively executed since it is executed before it is known whether or not its result is needed. There are potential hazards when speculatively executing instructions. If these hazards can be eliminated, the compiler can more aggressively schedule the code. The hazards of speculative execution are outlined in this paper. Three architectural models: restricted, general, and boosting, which have increasing amounts of support for removing these hazards are discussed. The performance gained by each level of additional hardware support is analyzed using the IMPACT C compiler which performs superblock scheduling for superscalar and superpipelined processors.
AB - To effectively exploit instruction level parallelism, the compiler must move instructions across branches. When an instruction is moved above a branch that it is control dependent on, it is considered to be speculatively executed since it is executed before it is known whether or not its result is needed. There are potential hazards when speculatively executing instructions. If these hazards can be eliminated, the compiler can more aggressively schedule the code. The hazards of speculative execution are outlined in this paper. Three architectural models: restricted, general, and boosting, which have increasing amounts of support for removing these hazards are discussed. The performance gained by each level of additional hardware support is analyzed using the IMPACT C compiler which performs superblock scheduling for superscalar and superpipelined processors.
KW - Conditional branches
KW - exception handling
KW - speculative execution
KW - static code scheduling
KW - superblock
KW - superpipelining
KW - superscalar
UR - http://www.scopus.com/inward/record.url?scp=0029289555&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0029289555&partnerID=8YFLogxK
U2 - 10.1109/12.376164
DO - 10.1109/12.376164
M3 - Article
AN - SCOPUS:0029289555
VL - 44
SP - 481
EP - 494
JO - IEEE Transactions on Computers
JF - IEEE Transactions on Computers
SN - 0018-9340
IS - 4
ER -