Three Architectural Models for Compiler-Controlled Speculative Execution

Pohua P. Chang, Nancy J. Warter, Scott A. Mahlke, William Y. Chen, Wen Mei W. Hwu

Research output: Contribution to journalArticle

Abstract

To effectively exploit instruction level parallelism, the compiler must move instructions across branches. When an instruction is moved above a branch that it is control dependent on, it is considered to be speculatively executed since it is executed before it is known whether or not its result is needed. There are potential hazards when speculatively executing instructions. If these hazards can be eliminated, the compiler can more aggressively schedule the code. The hazards of speculative execution are outlined in this paper. Three architectural models: restricted, general, and boosting, which have increasing amounts of support for removing these hazards are discussed. The performance gained by each level of additional hardware support is analyzed using the IMPACT C compiler which performs superblock scheduling for superscalar and superpipelined processors.

Original languageEnglish (US)
Pages (from-to)481-494
Number of pages14
JournalIEEE Transactions on Computers
Volume44
Issue number4
DOIs
StatePublished - Apr 1995

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Keywords

  • Conditional branches
  • exception handling
  • speculative execution
  • static code scheduling
  • superblock
  • superpipelining
  • superscalar

ASJC Scopus subject areas

  • Software
  • Theoretical Computer Science
  • Hardware and Architecture
  • Computational Theory and Mathematics

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