Thread-level speculation on a CMP can be energy efficient

Jose Renau; Karin Strauss; Luis Ceze; Wei Liu; Smruti Sarangi; James Tuck; Josep Torrellas

doi:10.1145/1088149.1088178

Thread-level speculation on a CMP can be energy efficient

Jose Renau, Karin Strauss, Luis Ceze, Wei Liu, Smruti Sarangi, James Tuck, Josep Torrellas

Research output: Contribution to conference › Paper

Abstract

Chip Multiprocessors (CMP) with Thread-Level Speculation (TLS) have become the subject of intense research. However, TLS is suspected of being too energy inefficient to compete against conventional processors. In this paper, we refute this claim. To do so, we first identify the main sources of dynamic energy consumption in TLS. Then, we present simple energy-saving optimizations that cut the energy cost of TLS by over 60% on average with minimal performance impact. The resulting TLS CMP, populated with four 3-issue cores, speeds-up full SPECint 2000 codes by 1.27 on average, while keeping the fraction of the chip's energy consumption due to TLS to only 20%. Compared to a 6-issue superscalar at the same frequency, the TLS CMP is on average faster, while consuming only 85% of its total on-chip power.

Original language	English (US)
Pages	219-228
Number of pages	10
DOIs	https://doi.org/10.1145/1088149.1088178
State	Published - Dec 1 2005
Event	ICS05 - 19th ACM International Conference on Supercomputing - Cambridge, MA, United States Duration: Jun 20 2005 → Jun 22 2005

Other

Other	ICS05 - 19th ACM International Conference on Supercomputing
Country	United States
City	Cambridge, MA
Period	6/20/05 → 6/22/05

ASJC Scopus subject areas

Computer Science(all)

Access to Document

10.1145/1088149.1088178

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Renau, J., Strauss, K., Ceze, L., Liu, W., Sarangi, S., Tuck, J., & Torrellas, J. (2005). Thread-level speculation on a CMP can be energy efficient. 219-228. Paper presented at ICS05 - 19th ACM International Conference on Supercomputing, Cambridge, MA, United States. https://doi.org/10.1145/1088149.1088178

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