TY - GEN
T1 - Thread Affinity in Software Transactional Memory
AU - Pasqualin, Douglas Pereira
AU - Diener, Matthias
AU - Du Bois, Andre Rauber
AU - Pilla, Mauricio Lima
N1 - Funding Information:
This study was financed in part by the Coordena¸cão de Aperfei¸coamento de Pessoal de Nível Superior - Brasil (CAPES) - Finance Code 001 and PROCAD/LEAPaD
Publisher Copyright:
© 2020 IEEE.
PY - 2020/7
Y1 - 2020/7
N2 - Software Transactional Memory (STM) is an abstraction to synchronize accesses to shared resources. It simplifies parallel programming by replacing the use of explicit locks and synchronization mechanisms with atomic blocks. A wellknown approach to improve performance of STM applications is to serialize transactions to avoid conflicts using schedulers and mapping algorithms. However, in current architectures with complex memory hierarchies it is also important to consider where the memory of the program is allocated and how it is accessed. An important technique for improving memory locality is to map threads and data of an application based on their memory access behavior. This technique is called sharing-aware mapping. In this paper, we introduce a method to detect sharing behavior directly inside the STM library by tracking and analyzing how threads perform STM operations. This information is then used to perform an optimized mapping of the application's threads to cores in order to improve the efficiency of STM operations. Experimental results with the STAMP benchmarks show performance gains of up to 9.7x (1.4x on average), and a reduction of the number of aborts of up to 8.5x, compared to the Linux scheduler.
AB - Software Transactional Memory (STM) is an abstraction to synchronize accesses to shared resources. It simplifies parallel programming by replacing the use of explicit locks and synchronization mechanisms with atomic blocks. A wellknown approach to improve performance of STM applications is to serialize transactions to avoid conflicts using schedulers and mapping algorithms. However, in current architectures with complex memory hierarchies it is also important to consider where the memory of the program is allocated and how it is accessed. An important technique for improving memory locality is to map threads and data of an application based on their memory access behavior. This technique is called sharing-aware mapping. In this paper, we introduce a method to detect sharing behavior directly inside the STM library by tracking and analyzing how threads perform STM operations. This information is then used to perform an optimized mapping of the application's threads to cores in order to improve the efficiency of STM operations. Experimental results with the STAMP benchmarks show performance gains of up to 9.7x (1.4x on average), and a reduction of the number of aborts of up to 8.5x, compared to the Linux scheduler.
KW - Multicore
KW - Sharing-aware
KW - Software Transactional Memory
KW - Thread Mapping
UR - http://www.scopus.com/inward/record.url?scp=85093096226&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85093096226&partnerID=8YFLogxK
U2 - 10.1109/ISPDC51135.2020.00033
DO - 10.1109/ISPDC51135.2020.00033
M3 - Conference contribution
AN - SCOPUS:85093096226
T3 - Proceedings - 2020 19th International Symposium on Parallel and Distributed Computing, ISPDC 2020
SP - 180
EP - 187
BT - Proceedings - 2020 19th International Symposium on Parallel and Distributed Computing, ISPDC 2020
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 19th International Symposium on Parallel and Distributed Computing, ISPDC 2020
Y2 - 5 July 2020 through 8 July 2020
ER -