Thread Affinity in Software Transactional Memory

Douglas Pereira Pasqualin, Matthias Diener, Andre Rauber Du Bois, Mauricio Lima Pilla

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Software Transactional Memory (STM) is an abstraction to synchronize accesses to shared resources. It simplifies parallel programming by replacing the use of explicit locks and synchronization mechanisms with atomic blocks. A wellknown approach to improve performance of STM applications is to serialize transactions to avoid conflicts using schedulers and mapping algorithms. However, in current architectures with complex memory hierarchies it is also important to consider where the memory of the program is allocated and how it is accessed. An important technique for improving memory locality is to map threads and data of an application based on their memory access behavior. This technique is called sharing-aware mapping. In this paper, we introduce a method to detect sharing behavior directly inside the STM library by tracking and analyzing how threads perform STM operations. This information is then used to perform an optimized mapping of the application's threads to cores in order to improve the efficiency of STM operations. Experimental results with the STAMP benchmarks show performance gains of up to 9.7x (1.4x on average), and a reduction of the number of aborts of up to 8.5x, compared to the Linux scheduler.

Original languageEnglish (US)
Title of host publicationProceedings - 2020 19th International Symposium on Parallel and Distributed Computing, ISPDC 2020
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages180-187
Number of pages8
ISBN (Electronic)9781728189468
DOIs
StatePublished - Jul 2020
Event19th International Symposium on Parallel and Distributed Computing, ISPDC 2020 - Warsaw, Poland
Duration: Jul 5 2020Jul 8 2020

Publication series

NameProceedings - 2020 19th International Symposium on Parallel and Distributed Computing, ISPDC 2020

Conference

Conference19th International Symposium on Parallel and Distributed Computing, ISPDC 2020
Country/TerritoryPoland
CityWarsaw
Period7/5/207/8/20

Keywords

  • Multicore
  • Sharing-aware
  • Software Transactional Memory
  • Thread Mapping

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Hardware and Architecture
  • Control and Optimization
  • Modeling and Simulation

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