Thickness measurement of ultra-thin gate dielectrics under inversion condition

W. J. Zhu; Mukesh Khare; J. Snare; P. R. Varekamp; S. H. Ku; P. Agnello; T. C. Chen; T. P. Ma

doi:10.1109/VTSA.2001.934522

Thickness measurement of ultra-thin gate dielectrics under inversion condition

W. J. Zhu
, Mukesh Khare
, J. Snare
, P. R. Varekamp
, S. H. Ku
, P. Agnello
, T. C. Chen
, T. P. Ma

Research output: Contribution to journal › Article › peer-review

Abstract

Accurate measurement of inversion thickness is essential in ULSI technology for development and control of ultra-thin gate dielectric processes. However, the accuracy of the measurement can be severely affected by the high gate leakage current and series resistance. This paper presents a methodology to reduce the measurement error by optimizing the ac modulation frequency and test device structures.

Original language	English (US)
Pages (from-to)	212-215
Number of pages	4
Journal	International Symposium on VLSI Technology, Systems, and Applications, Proceedings
DOIs	https://doi.org/10.1109/VTSA.2001.934522
State	Published - 2001
Externally published	Yes

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Electrical and Electronic Engineering

Online availability

10.1109/VTSA.2001.934522

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abstract = "Accurate measurement of inversion thickness is essential in ULSI technology for development and control of ultra-thin gate dielectric processes. However, the accuracy of the measurement can be severely affected by the high gate leakage current and series resistance. This paper presents a methodology to reduce the measurement error by optimizing the ac modulation frequency and test device structures.",

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AU - Zhu, W. J.

AU - Khare, Mukesh

AU - Snare, J.

AU - Varekamp, P. R.

AU - Ku, S. H.

AU - Agnello, P.

AU - Chen, T. C.

AU - Ma, T. P.

PY - 2001

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AB - Accurate measurement of inversion thickness is essential in ULSI technology for development and control of ultra-thin gate dielectric processes. However, the accuracy of the measurement can be severely affected by the high gate leakage current and series resistance. This paper presents a methodology to reduce the measurement error by optimizing the ac modulation frequency and test device structures.

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U2 - 10.1109/VTSA.2001.934522

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JO - International Symposium on VLSI Technology, Systems, and Applications, Proceedings

JF - International Symposium on VLSI Technology, Systems, and Applications, Proceedings

ER -

Thickness measurement of ultra-thin gate dielectrics under inversion condition

Abstract

ASJC Scopus subject areas

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