Thermally robust dual-work function ALD-MN x MOSFETs using conventional CMOS process flow

D. G. Park; Z. J. Luo; N. Edleman; W. Zhu; P. Nguyen; K. Wong; C. Cabral; P. Jamison; B. H. Lee; A. Chou; M. Chudzik; J. Bruley; O. Gluschenkov; P. Ronsheim; A. Chakravarti; R. Mitchell; V. Ku; H. Kim; E. Duch; P. Kozlowski; C. D'Emic; V. Narayanan; A. Steegen; R. Wise; R. Jammy; R. Rengarajan; H. Ng; A. Sekiguchi; C. H. Wann

Thermally robust dual-work function ALD-MN _x MOSFETs using conventional CMOS process flow

D. G. Park, Z. J. Luo, N. Edleman, W. Zhu, P. Nguyen, K. Wong, C. Cabral, P. Jamison, B. H. Lee, A. Chou, M. Chudzik, J. Bruley, O. Gluschenkov, P. Ronsheim, A. Chakravarti, R. Mitchell, V. Ku, H. Kim, E. Duch, P. KozlowskiC. D'Emic, V. Narayanan, A. Steegen, R. Wise, R. Jammy, R. Rengarajan, H. Ng, A. Sekiguchi, C. H. Wann

Research output: Contribution to journal › Conference article › peer-review

Abstract

Thermally stable dual work function metal gates are demonstrated using a conventional CMOS process flow. The gate structure consists of poly-Si/metal nitrides (MN _x)/ SiON (or high-k)/Si stack with atomic layer deposition (ALD)-TaN _x for the NFET and ALD-WN _x for the PFET. Much enhanced drive current (I _d) and transconductance (G _m) values, and reduced off current (I _off) characteristics were attained with ALD-MN _x gated devices over control poly-Si and PVD-MN _x devices within controllable V _t shifts. Excellent scalability of dual work function MN _x/high-k gate stack was demonstrated: the EOT was down to 6.6A° with low leakage in a low thermal budget device scheme.

Original language	English (US)
Pages (from-to)	186-187
Number of pages	2
Journal	Digest of Technical Papers - Symposium on VLSI Technology
State	Published - 2004
Externally published	Yes
Event	2004 Symposium on VLSI Technology - Digest of Technical Papers - Honolulu, HI, United States Duration: Jun 15 2004 → Jun 17 2004

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Electrical and Electronic Engineering

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Park, D. G., Luo, Z. J., Edleman, N., Zhu, W., Nguyen, P., Wong, K., Cabral, C., Jamison, P., Lee, B. H., Chou, A., Chudzik, M., Bruley, J., Gluschenkov, O., Ronsheim, P., Chakravarti, A., Mitchell, R., Ku, V., Kim, H., Duch, E., ... Wann, C. H. (2004). Thermally robust dual-work function ALD-MN _x MOSFETs using conventional CMOS process flow. Digest of Technical Papers - Symposium on VLSI Technology, 186-187.

Park, DG, Luo, ZJ, Edleman, N, Zhu, W, Nguyen, P, Wong, K, Cabral, C, Jamison, P, Lee, BH, Chou, A, Chudzik, M, Bruley, J, Gluschenkov, O, Ronsheim, P, Chakravarti, A, Mitchell, R, Ku, V, Kim, H, Duch, E, Kozlowski, P, D'Emic, C, Narayanan, V, Steegen, A, Wise, R, Jammy, R, Rengarajan, R, Ng, H, Sekiguchi, A & Wann, CH 2004, 'Thermally robust dual-work function ALD-MN _x MOSFETs using conventional CMOS process flow', Digest of Technical Papers - Symposium on VLSI Technology, pp. 186-187.

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title = "Thermally robust dual-work function ALD-MN x MOSFETs using conventional CMOS process flow",

abstract = "Thermally stable dual work function metal gates are demonstrated using a conventional CMOS process flow. The gate structure consists of poly-Si/metal nitrides (MN x)/ SiON (or high-k)/Si stack with atomic layer deposition (ALD)-TaN x for the NFET and ALD-WN x for the PFET. Much enhanced drive current (I d) and transconductance (G m) values, and reduced off current (I off) characteristics were attained with ALD-MN x gated devices over control poly-Si and PVD-MN x devices within controllable V t shifts. Excellent scalability of dual work function MN x/high-k gate stack was demonstrated: the EOT was down to 6.6A° with low leakage in a low thermal budget device scheme.",

author = "Park, {D. G.} and Luo, {Z. J.} and N. Edleman and W. Zhu and P. Nguyen and K. Wong and C. Cabral and P. Jamison and Lee, {B. H.} and A. Chou and M. Chudzik and J. Bruley and O. Gluschenkov and P. Ronsheim and A. Chakravarti and R. Mitchell and V. Ku and H. Kim and E. Duch and P. Kozlowski and C. D'Emic and V. Narayanan and A. Steegen and R. Wise and R. Jammy and R. Rengarajan and H. Ng and A. Sekiguchi and Wann, {C. H.}",

year = "2004",

language = "English (US)",

pages = "186--187",

journal = "Digest of Technical Papers - Symposium on VLSI Technology",

issn = "0743-1562",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "2004 Symposium on VLSI Technology - Digest of Technical Papers ; Conference date: 15-06-2004 Through 17-06-2004",

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TY - JOUR

T1 - Thermally robust dual-work function ALD-MN x MOSFETs using conventional CMOS process flow

AU - Park, D. G.

AU - Luo, Z. J.

AU - Edleman, N.

AU - Zhu, W.

AU - Nguyen, P.

AU - Wong, K.

AU - Cabral, C.

AU - Jamison, P.

AU - Lee, B. H.

AU - Chou, A.

AU - Chudzik, M.

AU - Bruley, J.

AU - Gluschenkov, O.

AU - Ronsheim, P.

AU - Chakravarti, A.

AU - Mitchell, R.

AU - Ku, V.

AU - Kim, H.

AU - Duch, E.

AU - Kozlowski, P.

AU - D'Emic, C.

AU - Narayanan, V.

AU - Steegen, A.

AU - Wise, R.

AU - Jammy, R.

AU - Rengarajan, R.

AU - Ng, H.

AU - Sekiguchi, A.

AU - Wann, C. H.

PY - 2004

Y1 - 2004

N2 - Thermally stable dual work function metal gates are demonstrated using a conventional CMOS process flow. The gate structure consists of poly-Si/metal nitrides (MN x)/ SiON (or high-k)/Si stack with atomic layer deposition (ALD)-TaN x for the NFET and ALD-WN x for the PFET. Much enhanced drive current (I d) and transconductance (G m) values, and reduced off current (I off) characteristics were attained with ALD-MN x gated devices over control poly-Si and PVD-MN x devices within controllable V t shifts. Excellent scalability of dual work function MN x/high-k gate stack was demonstrated: the EOT was down to 6.6A° with low leakage in a low thermal budget device scheme.

AB - Thermally stable dual work function metal gates are demonstrated using a conventional CMOS process flow. The gate structure consists of poly-Si/metal nitrides (MN x)/ SiON (or high-k)/Si stack with atomic layer deposition (ALD)-TaN x for the NFET and ALD-WN x for the PFET. Much enhanced drive current (I d) and transconductance (G m) values, and reduced off current (I off) characteristics were attained with ALD-MN x gated devices over control poly-Si and PVD-MN x devices within controllable V t shifts. Excellent scalability of dual work function MN x/high-k gate stack was demonstrated: the EOT was down to 6.6A° with low leakage in a low thermal budget device scheme.

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M3 - Conference article

AN - SCOPUS:4544325618

SN - 0743-1562

SP - 186

EP - 187

JO - Digest of Technical Papers - Symposium on VLSI Technology

JF - Digest of Technical Papers - Symposium on VLSI Technology

T2 - 2004 Symposium on VLSI Technology - Digest of Technical Papers

Y2 - 15 June 2004 through 17 June 2004

ER -

Thermally robust dual-work function ALD-MN _x MOSFETs using conventional CMOS process flow

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