@inproceedings{6ffc9f1e6f7641f29ed5961b9822f14c,
title = "Thermal-Aware SoC Macro Placement and Multi-chip Module Design Optimization with Bayesian Optimization",
abstract = "The effect of temperature on the reliability and performance of electrical components and integrated circuits warrants the inclusion of thermal considerations in the early stages of electronic system design. However, the many design parameters involved in the design of the package and the die or macro placement, along with the use of expensive thermal simulations, poses difficulty for conventional optimization algorithms. To overcome that hurdle, this work proposes an efficient Bayesian optimization algorithm which is demonstrated for two early-stage design problems. First, the proposed algorithm is used for the thermal-aware placement of macros with a variable aspect ratio. Second, the proposed Bayesian optimization algorithm is utilized in a two-stage process to optimize the die placement and the package design parameters of a multi-chip module.",
keywords = "Bayesian optimization, Die placement, Floor-planning, Macro Placement, Multi-Chip Module",
author = "Michael Molter and Rahul Kumar and Sonja Koller and Bhatti, {Osama Waqar} and Nikita Ambasana and Elyse Rosenbaum and Madhavan Swaminathan",
note = "Publisher Copyright: {\textcopyright} 2023 IEEE.; 73rd IEEE Electronic Components and Technology Conference, ECTC 2023 ; Conference date: 30-05-2023 Through 02-06-2023",
year = "2023",
doi = "10.1109/ECTC51909.2023.00160",
language = "English (US)",
series = "Proceedings - Electronic Components and Technology Conference",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "935--942",
booktitle = "Proceedings - IEEE 73rd Electronic Components and Technology Conference, ECTC 2023",
address = "United States",
}