Analog to digital conversion is often a critical component of a digital communication link. However, the designs of typical architectures for analog to digital converters (ADCs) are focused primarily on signal reconstruction rather than gathering information for the reliable detection of symbols sent through a channel. Therefore, we consider new architectures for statistics gathering converters (SGCs), and demonstrate that these architectures achieve good communication performance while removing the artificial constraints imposed by the typical ADC design metrics. For a particular architecture, we examine various metrics for converter performance that are tightly coupled with the intended use of the component - digital communications. These include mutual information per input symbol, linear minimum mean square error, and bit error rate. The architecture consists of a bank of statistics samplers, where each of these samplers is a simple low power passive linear circuit network followed by a traditional periodic sampler. We compare the performance of this converter front-end to a more traditional ADC front-end, with respect to the system level metrics. We show that, whereas traditional ADC performance metrics would indicate poor performance of statistics gathering converters, the application aligned system metrics, on the contrary, indicate favorable performance compared with traditional ADCs.