The Pensieve project: A compiler infrastructure for memory models

Chi Leung Wong, Zehra Sura, Xing Fang, S. P. Midkiff, Jaejin Lee, D. Padua

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The design of memory consistency models for both hardware and software is a difficult task. It is particularly difficult for a programming language because the target audience is much wider than the target audience for a machine language, making usability a more important criterion. Adding to this problem is the fact that the programming language community has little experience with designing programming language consistency models, and therefore each new attempt is very much a voyage into uncharted territory. A concrete example of the difficulties of the task is the current Java memory model. Although designed to be easy to use by Java programmers, it is poorly understood, and at least one common idiom (the "double-check idiom") to exploit the model is unsafe. In this paper, we describe the design of an optimizing Java compiler that accepts, as either input or as an interface implementation, a consistency model for the code to be compiled. The compiler uses escape analysis, D. Shasha and M. Snir's (1988) delay set analysis, and our own CSSA (concurrent static single assignment) program representation to normalize the effects of different consistency models on optimizations and analysis. The compiler is intended to serve as a testbed to prototype new memory models and to measure the differences between different memory models in terms of program performance.

Original languageEnglish (US)
Title of host publicationProceedings - International Symposium on Parallel Architectures, Algorithms and Networks, I-SPAN 2002
EditorsD. Frank Hsu, Rafael P. Saldana, Oscar H. Ibarra
PublisherIEEE Computer Society
Pages239-244
Number of pages6
ISBN (Electronic)0769515797
DOIs
StatePublished - 2002
EventInternational Symposium on Parallel Architectures, Algorithms and Networks, I-SPAN 2002 - Makati, Manila, Philippines
Duration: May 22 2002May 24 2002

Publication series

NameProceedings of the International Symposium on Parallel Architectures, Algorithms and Networks, I-SPAN
Volume2002-January

Other

OtherInternational Symposium on Parallel Architectures, Algorithms and Networks, I-SPAN 2002
Country/TerritoryPhilippines
CityMakati, Manila
Period5/22/025/24/02

Keywords

  • Computer languages
  • Concrete
  • Delay effects
  • Design optimization
  • Hardware
  • Java
  • Optimizing compilers
  • Program processors
  • Programming profession
  • Usability

ASJC Scopus subject areas

  • General Computer Science

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