TY - JOUR
T1 - The Need for Fast Communication in Hardware-Based Speculative Chip Multiprocessors
AU - Krishnan, Venkata
AU - Torrellas, Josep
N1 - Funding Information:
We thank the referees and the members of the I-ACOMA group for their valuable feedback. This work was supported in part by the National Science Foundation under grants NSF Young Investigator Award MIP-9457436, ASC-9612099, and MIP-9619351, DARPA Contract DABT63-95-C-0097, and gifts from IBM and Intel.
Copyright:
Copyright 2005 Elsevier Science B.V., Amsterdam. All rights reserved.
PY - 2001
Y1 - 2001
N2 - Chip-multiprocessor (CMP) architectures are a promising design alternative to exploit the ever-increasing number of transistors that can be put on a die. To deliver high performance on applications that cannot be easily parallelized, CMPs can use additional support for speculatively executing the possibly data-dependent threads of an application. For cross-thread dependences that must be handled dynamically, the threads can be made to synchronize and communicate either at the register level or at the memory level. In the past, it has been unclear whether the higher hardware cost of register-level communication is cost-effective. In this paper, we show that the wide-issue dynamic processors that will soon populate CMPs, make fast communication a requirement for high performance. Consequently, we propose an effective hardware mechanism to support communication and synchronization of registers between on-chip processors. Our scheme adds enough support to enable register-level communication without specializing the architecture toward speculation much. Finally, our scheme allows the system to achieve near ideal performance.
AB - Chip-multiprocessor (CMP) architectures are a promising design alternative to exploit the ever-increasing number of transistors that can be put on a die. To deliver high performance on applications that cannot be easily parallelized, CMPs can use additional support for speculatively executing the possibly data-dependent threads of an application. For cross-thread dependences that must be handled dynamically, the threads can be made to synchronize and communicate either at the register level or at the memory level. In the past, it has been unclear whether the higher hardware cost of register-level communication is cost-effective. In this paper, we show that the wide-issue dynamic processors that will soon populate CMPs, make fast communication a requirement for high performance. Consequently, we propose an effective hardware mechanism to support communication and synchronization of registers between on-chip processors. Our scheme adds enough support to enable register-level communication without specializing the architecture toward speculation much. Finally, our scheme allows the system to achieve near ideal performance.
KW - Chip-multiprocessor
KW - Data-dependence speculation
KW - Inter-thread communication
KW - Speculative multithreading
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U2 - 10.1023/A:1026479803767
DO - 10.1023/A:1026479803767
M3 - Article
AN - SCOPUS:0042281592
SN - 0885-7458
VL - 29
SP - 3
EP - 33
JO - International Journal of Parallel Programming
JF - International Journal of Parallel Programming
IS - 1
ER -