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The latency insertion method for simulations of phase-locked loops
P. Goh,
J. E. Schutt-Ainé
Electrical and Computer Engineering
Coordinated Science Lab
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Keyphrases
Phase-locked Loop
100%
Latency Insertion Method
100%
Analytical Solution
20%
Behavioral Level
20%
Transistor Level
20%
Simulation Method
20%
Transient Response
20%
Behavioral Model
20%
Dynamic Response
20%
Latency
20%
Discretization Scheme
20%
Pullout
20%
Model-based Simulation
20%
Simulation Approach
20%
Spices
20%
Behavioral Simulation
20%
Phase-locked Loop Dynamics
20%
Engineering
Phase Locked Loop
100%
SPICE
14%
Simulation Method
14%
Transient Analysis
14%
Dynamic Response
14%
Discretization Scheme
14%
Behavioral Model
14%
Loop Dynamic
14%
Earth and Planetary Sciences
Dynamic Response
100%
Material Science
Transistor
100%
Biochemistry, Genetics and Molecular Biology
Solution and Solubility
100%