The interconnect bottleneck in multi-GHz processors; New opportunities for hybrid electrical/optical solutions

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The semiconductor industry appears to be confident that, even without any major breakthroughs in photolithography, it will be able to achieve device feature sizes in the order of 100 nm by the year 2006. This reduction in feature size implies significantly higher device switching speeds and faster circuits. More specifically, microprocessors with 3 GHz on-chip clock frequency are within reach by the year 2006. The only obstacle to such an impressive level of performance, both across the chip and beyond the chip at the system level, is the availability of an interconnection network of unprecedented complexity and capable of supporting multi-GHz-bandwidth, distortion- and interference-free propagation both on-chip and off-chip. This interconnect bottleneck to multi-GHz processor realization is examined in this paper The emphasis is on the evaluation of the most promising and cost-effective electrical ways of overcoming this bottleneck. It is argued that some of these potential solutions involve technologies that are compatible with on-going developments in optical interconnects. Thus, an opportunity is identified for bringing together electrical and optical interconnect technologies at a level in the integration hierarchy where traditionally optics is considered to be at a disadvantage, namely, at the chip and chip-to-package interconnect level.

Original languageEnglish (US)
Title of host publicationProceedings - 5th International Conference on Massively Parallel Processing, MPPOI 1998
EditorsMarc Snir, Lennart Johnsson, Ray Kostuck, Eugen Schenfeld
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages96-105
Number of pages10
ISBN (Print)0818685727, 9780818685729
DOIs
StatePublished - Jan 1 1998
Event5th International Conference on Massively Parallel Processing, MPPOI 1998 - Las Vegas, United States
Duration: Jun 15 1998Jun 17 1998

Publication series

NameProceedings - 5th International Conference on Massively Parallel Processing, MPPOI 1998

Other

Other5th International Conference on Massively Parallel Processing, MPPOI 1998
CountryUnited States
CityLas Vegas
Period6/15/986/17/98

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Hardware and Architecture

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