The impact of technology scaling on lifetime reliability

Jayanth Srinivasan, Sarita V. Adve, Pradip Bose, Jude A. Rivers

Research output: Contribution to conferencePaper

Abstract

The relentless scaling of CMOS technology has provided a steady increase in processor performance for the past three decades. However, increased power densities (hence temperatures) and other scaling effects have an adverse impact on long-term processor lifetime reliability. This paper represents a first attempt at quantifying the impact of scaling on lifetime reliability due to intrinsic hard errors, taking workload characteristics into consideration. For our quantitative evaluation, we use RAMP, a previously proposed industrial-strength model that provides reliability estimates for a workload, but for a given technology. We extend RAMP by adding scaling specific parameters to enable workload-dependent lifetime reliability evaluation at different technologies. We show that (1) scaling has a significant impact on processor hard failure rates - on average, with SPEC benchmarks, we find the failure rate of a scaled 65nm processor to be 316% higher than a similarly pipelined 180nm processor; (2) time-dependent dielectric breakdown and electromigration have the largest increases; and (3) with scaling, the difference in reliability from running at worst-case vs. typical workload operating conditions increases significantly, as does the difference from running different workloads. Our results imply that leveraging a single microarchitecture design for multiple remaps across a few technology generations will become increasingly difficult, and motivate a need for workload specific, microarchitectural lifetime reliability awareness at an early design stage.

Original languageEnglish (US)
Pages177-186
Number of pages10
StatePublished - Oct 1 2004
Event2004 International Conference on Dependable Systems and Networks - Florence, Italy
Duration: Jun 28 2004Jul 1 2004

Other

Other2004 International Conference on Dependable Systems and Networks
CountryItaly
CityFlorence
Period6/28/047/1/04

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Computer Networks and Communications

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  • Cite this

    Srinivasan, J., Adve, S. V., Bose, P., & Rivers, J. A. (2004). The impact of technology scaling on lifetime reliability. 177-186. Paper presented at 2004 International Conference on Dependable Systems and Networks, Florence, Italy.