The energy efficiency of CMP vs. SMT for multimedia workloads

Ruchira Sasanka, Sarita V Adve, Yen Kuang Chen, Eric Debes

Research output: Contribution to conferencePaper

Abstract

This paper compares the energy efficiency of chip multiprocessing (CMP) and simultaneous multithreading (SMT) on modern out-of-order processors for the increasingly important multimedia applications. Since performance is an important metric for real-time multimedia applications, we compare configurations at equal performance. We perform this comparison for a large number of performance points derived using different processor architectures and frequencies/voltages. We find that for the design space explored, for each workload, at each performance point, CMP is more energy efficient than SMT. The difference is small for two thread systems, but large (18% to 44%) for four thread systems. We also find that the best SMT and the best CMP configuration for a given performance target have different architecture and frequency/voltage. Therefore, their relative energy efficiency depends on a subtle interplay between various factors such as capacitance, voltage, IPC, frequency, and the level of clock gating, as well as workload features. We perform a detailed analysis considering these factors and develop a mathematical model to explain these results. Although CMP shows a clear energy advantage for four-thread (and higher) workloads, it comes at the cost of increased silicon area. We therefore investigate a hybrid solution where a CMP is built out of SMT cores, and find it to be an effective compromise. Finally, we find that we can reduce energy further for CMP with a straightforward application of previously proposed techniques of adaptive architectures and dynamic voltage/frequency scaling. CMP, SMT, Energy Efficiency, Multimedia.

Original languageEnglish (US)
Pages196-206
Number of pages11
StatePublished - Nov 22 2004
Event2004 International Conference on Supercomputing - Saint-Malo, France
Duration: Jun 26 2004Jul 1 2004

Other

Other2004 International Conference on Supercomputing
CountryFrance
CitySaint-Malo
Period6/26/047/1/04

Fingerprint

Energy efficiency
Electric potential
Clocks
Capacitance
Mathematical models
Silicon

ASJC Scopus subject areas

  • Computer Science(all)

Cite this

Sasanka, R., Adve, S. V., Chen, Y. K., & Debes, E. (2004). The energy efficiency of CMP vs. SMT for multimedia workloads. 196-206. Paper presented at 2004 International Conference on Supercomputing, Saint-Malo, France.

The energy efficiency of CMP vs. SMT for multimedia workloads. / Sasanka, Ruchira; Adve, Sarita V; Chen, Yen Kuang; Debes, Eric.

2004. 196-206 Paper presented at 2004 International Conference on Supercomputing, Saint-Malo, France.

Research output: Contribution to conferencePaper

Sasanka, R, Adve, SV, Chen, YK & Debes, E 2004, 'The energy efficiency of CMP vs. SMT for multimedia workloads' Paper presented at 2004 International Conference on Supercomputing, Saint-Malo, France, 6/26/04 - 7/1/04, pp. 196-206.
Sasanka R, Adve SV, Chen YK, Debes E. The energy efficiency of CMP vs. SMT for multimedia workloads. 2004. Paper presented at 2004 International Conference on Supercomputing, Saint-Malo, France.
Sasanka, Ruchira ; Adve, Sarita V ; Chen, Yen Kuang ; Debes, Eric. / The energy efficiency of CMP vs. SMT for multimedia workloads. Paper presented at 2004 International Conference on Supercomputing, Saint-Malo, France.11 p.
@conference{0204dcca5cfb4171b641aad335567a15,
title = "The energy efficiency of CMP vs. SMT for multimedia workloads",
abstract = "This paper compares the energy efficiency of chip multiprocessing (CMP) and simultaneous multithreading (SMT) on modern out-of-order processors for the increasingly important multimedia applications. Since performance is an important metric for real-time multimedia applications, we compare configurations at equal performance. We perform this comparison for a large number of performance points derived using different processor architectures and frequencies/voltages. We find that for the design space explored, for each workload, at each performance point, CMP is more energy efficient than SMT. The difference is small for two thread systems, but large (18{\%} to 44{\%}) for four thread systems. We also find that the best SMT and the best CMP configuration for a given performance target have different architecture and frequency/voltage. Therefore, their relative energy efficiency depends on a subtle interplay between various factors such as capacitance, voltage, IPC, frequency, and the level of clock gating, as well as workload features. We perform a detailed analysis considering these factors and develop a mathematical model to explain these results. Although CMP shows a clear energy advantage for four-thread (and higher) workloads, it comes at the cost of increased silicon area. We therefore investigate a hybrid solution where a CMP is built out of SMT cores, and find it to be an effective compromise. Finally, we find that we can reduce energy further for CMP with a straightforward application of previously proposed techniques of adaptive architectures and dynamic voltage/frequency scaling. CMP, SMT, Energy Efficiency, Multimedia.",
author = "Ruchira Sasanka and Adve, {Sarita V} and Chen, {Yen Kuang} and Eric Debes",
year = "2004",
month = "11",
day = "22",
language = "English (US)",
pages = "196--206",
note = "2004 International Conference on Supercomputing ; Conference date: 26-06-2004 Through 01-07-2004",

}

TY - CONF

T1 - The energy efficiency of CMP vs. SMT for multimedia workloads

AU - Sasanka, Ruchira

AU - Adve, Sarita V

AU - Chen, Yen Kuang

AU - Debes, Eric

PY - 2004/11/22

Y1 - 2004/11/22

N2 - This paper compares the energy efficiency of chip multiprocessing (CMP) and simultaneous multithreading (SMT) on modern out-of-order processors for the increasingly important multimedia applications. Since performance is an important metric for real-time multimedia applications, we compare configurations at equal performance. We perform this comparison for a large number of performance points derived using different processor architectures and frequencies/voltages. We find that for the design space explored, for each workload, at each performance point, CMP is more energy efficient than SMT. The difference is small for two thread systems, but large (18% to 44%) for four thread systems. We also find that the best SMT and the best CMP configuration for a given performance target have different architecture and frequency/voltage. Therefore, their relative energy efficiency depends on a subtle interplay between various factors such as capacitance, voltage, IPC, frequency, and the level of clock gating, as well as workload features. We perform a detailed analysis considering these factors and develop a mathematical model to explain these results. Although CMP shows a clear energy advantage for four-thread (and higher) workloads, it comes at the cost of increased silicon area. We therefore investigate a hybrid solution where a CMP is built out of SMT cores, and find it to be an effective compromise. Finally, we find that we can reduce energy further for CMP with a straightforward application of previously proposed techniques of adaptive architectures and dynamic voltage/frequency scaling. CMP, SMT, Energy Efficiency, Multimedia.

AB - This paper compares the energy efficiency of chip multiprocessing (CMP) and simultaneous multithreading (SMT) on modern out-of-order processors for the increasingly important multimedia applications. Since performance is an important metric for real-time multimedia applications, we compare configurations at equal performance. We perform this comparison for a large number of performance points derived using different processor architectures and frequencies/voltages. We find that for the design space explored, for each workload, at each performance point, CMP is more energy efficient than SMT. The difference is small for two thread systems, but large (18% to 44%) for four thread systems. We also find that the best SMT and the best CMP configuration for a given performance target have different architecture and frequency/voltage. Therefore, their relative energy efficiency depends on a subtle interplay between various factors such as capacitance, voltage, IPC, frequency, and the level of clock gating, as well as workload features. We perform a detailed analysis considering these factors and develop a mathematical model to explain these results. Although CMP shows a clear energy advantage for four-thread (and higher) workloads, it comes at the cost of increased silicon area. We therefore investigate a hybrid solution where a CMP is built out of SMT cores, and find it to be an effective compromise. Finally, we find that we can reduce energy further for CMP with a straightforward application of previously proposed techniques of adaptive architectures and dynamic voltage/frequency scaling. CMP, SMT, Energy Efficiency, Multimedia.

UR - http://www.scopus.com/inward/record.url?scp=8344233355&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=8344233355&partnerID=8YFLogxK

M3 - Paper

AN - SCOPUS:8344233355

SP - 196

EP - 206

ER -