Abstract
Two compiler-assisted multiple-instruction word retry schemes for very long instruction word (VLIW) architectures are described. The first scheme compacts the compiler-generated hazard-free code with different degrees of rollback capability for scalar processors, and inserts no-ops in the scheduled code words. The second scheme employs a hardware read buffer to resolve frequently occurring data hazards, and utilizes the compiler to resolve the remaining hazards.
| Original language | English (US) |
|---|---|
| Title of host publication | Proceedings of IEEE Workshop on Fault-Tolerant Parallel and Distributed Systems, FTPDS 1994 |
| Editors | Dhiraj Pradhan, Dimiter Avresky |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 51-58 |
| Number of pages | 8 |
| ISBN (Electronic) | 0818668075, 9780818668074 |
| DOIs | |
| State | Published - Jan 1 1994 |
| Event | 1994 IEEE Workshop on Fault-Tolerant Parallel and Distributed Systems, FTPDS 1994 - College Station, United States Duration: Jun 12 1994 → Jun 14 1994 |
Publication series
| Name | Proceedings of IEEE Workshop on Fault-Tolerant Parallel and Distributed Systems, FTPDS 1994 |
|---|
Conference
| Conference | 1994 IEEE Workshop on Fault-Tolerant Parallel and Distributed Systems, FTPDS 1994 |
|---|---|
| Country | United States |
| City | College Station |
| Period | 6/12/94 → 6/14/94 |
Fingerprint
ASJC Scopus subject areas
- Computer Networks and Communications
- Hardware and Architecture
- Safety, Risk, Reliability and Quality
Cite this
The application of compiler-assisted multiple-instruction retry to VLIW architectures. / Chen, Shyh Kwei; Fuchs, W. K.; Hwu, Wen-Mei W.
Proceedings of IEEE Workshop on Fault-Tolerant Parallel and Distributed Systems, FTPDS 1994. ed. / Dhiraj Pradhan; Dimiter Avresky. Institute of Electrical and Electronics Engineers Inc., 1994. p. 51-58 494474 (Proceedings of IEEE Workshop on Fault-Tolerant Parallel and Distributed Systems, FTPDS 1994).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - The application of compiler-assisted multiple-instruction retry to VLIW architectures
AU - Chen, Shyh Kwei
AU - Fuchs, W. K.
AU - Hwu, Wen-Mei W
PY - 1994/1/1
Y1 - 1994/1/1
N2 - Two compiler-assisted multiple-instruction word retry schemes for very long instruction word (VLIW) architectures are described. The first scheme compacts the compiler-generated hazard-free code with different degrees of rollback capability for scalar processors, and inserts no-ops in the scheduled code words. The second scheme employs a hardware read buffer to resolve frequently occurring data hazards, and utilizes the compiler to resolve the remaining hazards.
AB - Two compiler-assisted multiple-instruction word retry schemes for very long instruction word (VLIW) architectures are described. The first scheme compacts the compiler-generated hazard-free code with different degrees of rollback capability for scalar processors, and inserts no-ops in the scheduled code words. The second scheme employs a hardware read buffer to resolve frequently occurring data hazards, and utilizes the compiler to resolve the remaining hazards.
UR - http://www.scopus.com/inward/record.url?scp=85063519702&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85063519702&partnerID=8YFLogxK
U2 - 10.1109/FTPDS.1994.494474
DO - 10.1109/FTPDS.1994.494474
M3 - Conference contribution
AN - SCOPUS:85063519702
T3 - Proceedings of IEEE Workshop on Fault-Tolerant Parallel and Distributed Systems, FTPDS 1994
SP - 51
EP - 58
BT - Proceedings of IEEE Workshop on Fault-Tolerant Parallel and Distributed Systems, FTPDS 1994
A2 - Pradhan, Dhiraj
A2 - Avresky, Dimiter
PB - Institute of Electrical and Electronics Engineers Inc.
ER -