The application of compiler-assisted multiple-instruction retry to VLIW architectures

Shyh Kwei Chen, W. K. Fuchs, W. M.W. Hwu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Two compiler-assisted multiple-instruction word retry schemes for very long instruction word (VLIW) architectures are described. The first scheme compacts the compiler-generated hazard-free code with different degrees of rollback capability for scalar processors, and inserts no-ops in the scheduled code words. The second scheme employs a hardware read buffer to resolve frequently occurring data hazards, and utilizes the compiler to resolve the remaining hazards.

Original languageEnglish (US)
Title of host publicationProceedings of IEEE Workshop on Fault-Tolerant Parallel and Distributed Systems, FTPDS 1994
EditorsDhiraj Pradhan, Dimiter Avresky
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages51-58
Number of pages8
ISBN (Electronic)0818668075, 9780818668074
DOIs
StatePublished - Jan 1 1994
Event1994 IEEE Workshop on Fault-Tolerant Parallel and Distributed Systems, FTPDS 1994 - College Station, United States
Duration: Jun 12 1994Jun 14 1994

Publication series

NameProceedings of IEEE Workshop on Fault-Tolerant Parallel and Distributed Systems, FTPDS 1994

Conference

Conference1994 IEEE Workshop on Fault-Tolerant Parallel and Distributed Systems, FTPDS 1994
CountryUnited States
CityCollege Station
Period6/12/946/14/94

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Hardware and Architecture
  • Safety, Risk, Reliability and Quality

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