Temporally synchronized emulation of devices with simulation of networks

We describe a platform that uses temporally integrated co-simulation of emulated devices and simulation of networks that connect them, for activities such as performance evaluation and resilience assessment. In our approach all emulated and simulated components are time-synchronized to a virtual clock. We propose and study an approach which uses compiler analysis to augment emulated code with logic for precise instruction level tracking of execution paths. This is combined with a mechanism to ascribe virtual time for each execution burst based on the sequence of executed instructions. The overhead of synchronization between emulated components and simulated components is reduced by compiler-based identification of "lookahead", which identifies epochs of emulated execution during which a process can be predicted to act independently of any other. Through evaluations, we show that our approach enables fast and repeatable execution of co-simulated models.