Temperature Mapping of Stacked Silicon Dies from X-Ray-Diffraction Intensities

Darshan Chalise, Peter Kenesei, Sarvjit D. Shastri, David G. Cahill

Research output: Contribution to journalArticlepeer-review


Increasing power densities in integrated circuits have led to an increased prevalence of thermal hotspots in integrated circuits. Tracking these thermal hotspots is imperative to prevent circuit failures. In three-dimensional (3D) integrated circuits, conventional surface techniques like infrared thermometry are unable to measure the 3D temperature distribution, and optical and magnetic resonance techniques are difficult to apply due to the presence of metals and large current densities. X-rays offer a high penetration depth and can be used to probe 3D structures. We report a method utilizing the temperature dependence of x-ray-diffraction intensity via the Debye-Waller factor to simultaneously map the temperature of individual silicon dies in a stack. Utilizing beamline 1-ID-E at the Advanced Photon Source (Argonne), we demonstrate, for each individual silicon die, a temperature resolution of 3 K, a spatial resolution of 100 × 400 μm2, and a temporal resolution of 20 s. Utilizing a sufficiently high-intensity laboratory source, e.g., from a liquid-anode source, this method can be scaled down to laboratories for noninvasive temperature mapping of 3D integrated circuits.

Original languageEnglish (US)
Article number014076
JournalPhysical Review Applied
Issue number1
StatePublished - Jul 2022

ASJC Scopus subject areas

  • General Physics and Astronomy


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