System-level routing of mixed-signal ASICs in WREN

Sujoy Mitra, Sudip K. Nag, Rob A. Rutenbar, L. Richard Carley

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper presents new techniques for global and detailed routing of the macrocell-style analog core of a mixed-signal ASIC. We combine a comparatively simple geometric model of the problem with an aggressive simulated annealing formulation that selects paths while accommodating numerous signal-integrity constraints. Experimental results demonstrate that it is critical to attack such constraints both globally (system-level) and locally (channel-level) to meet designer-specified performance targets.

Original languageEnglish (US)
Title of host publicationIEEE/ACM International Conference on Computer-Aided Design
PublisherPubl by IEEE
Pages394-399
Number of pages6
ISBN (Print)0818630108, 9780818630101
DOIs
StatePublished - 1992
Externally publishedYes
EventIEEE/ACM International Conference on Computer-Aided Design - ICCAD '92 - Santa Clara, CA, USA
Duration: Nov 8 1992Nov 12 1992

Publication series

NameIEEE/ACM International Conference on Computer-Aided Design

Other

OtherIEEE/ACM International Conference on Computer-Aided Design - ICCAD '92
CitySanta Clara, CA, USA
Period11/8/9211/12/92

ASJC Scopus subject areas

  • General Engineering

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