System-level optimization of switched-capacitor VRM and core for sub/near-Vt computing

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This brief proposes to jointly optimize a switched capacitor voltage regulator module (SC-VRM) combined with a compute core to minimize system energy per instruction. Past work seeking to optimize system energy efficiency has focused on separately maximizing SC-VRM efficiency or operating the compute core at its minimum energy operating point (MEOP). We first propose and verify a core-aware SC-VRM energy model, which explicitly accounts for throughput constraints. Second, we perform joint optimization considering throughput unconstrained applications (TUA) and throughput constrained applications (TCAs). We show that, for TUA, the system MEOP (S-MEOP) voltage is different from both the core MEOP (C-MEOP) and VRM maximum efficiency point (V-MEP) voltages, and operating at S-MEOP achieves 12.3% and 21.8% energy savings compared with C-MEOP and V-MEP, respectively. For TCA, S-MEOP is achieved at the same voltage as C-MEOP but different from the voltage for V-MEP, and 38.9% energy savings can be obtained by operating at S-MEOP.

Original languageEnglish (US)
Article number6837454
Pages (from-to)726-730
Number of pages5
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Issue number9
StatePublished - Sep 1 2014


  • DC-DC power converters
  • design optimization
  • integrated circuit modeling
  • switched-mode power supply

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


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