System design of a low-power I/O link

Srinivasa R. Sridhara, Ganesh Balamurugan, Naresh R Shanbhag

Research output: Contribution to journalConference articlepeer-review


In this paper, we present a detailed analysis of the system design choices available for low-power high-speed I/O link transceivers. Using the transceiver power dissipation as the metric, we compare three equalization schemes (linear equalizer, decision-feedback equalizer, and transmit pre-emphasis) in combination with three pulse amplitude modulation (PAM) schemes (2-PAM, 4-PAM, and 8-PAM). The input signal levels and the filter lengths in the equalizer are chosen to minimize the power dissipation while meeting a bit error rate constraint. We show that, for a typical 20″ intersymbol interference dominated link, transmit pre-emphasis in combination with 4-PAM results in 75data rates.

Original languageEnglish (US)
Pages (from-to)1468-1472
Number of pages5
JournalConference Record of the Asilomar Conference on Signals, Systems and Computers
StatePublished - 2003
EventConference Record of the Thirty-Seventh Asilomar Conference on Signals, Systems and Computers - Pacific Grove, CA, United States
Duration: Nov 9 2003Nov 12 2003

ASJC Scopus subject areas

  • Signal Processing
  • Computer Networks and Communications


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