Debugging the pre-Silicon Register Transfer Level (RTL) design is one of the most resource and time intensive processes in contemporary hardware design cycles. Given the scale and complexity of designs, bug localization is very valuable for debugging. We present an automatic bug localization technique in RTL. Our technique is based on identifying statistically relevant common symptoms across failing simulation traces through mining, and mapping these back to the corresponding execution paths in the RTL source code. Our localized code zones are small, focused, functionally coherent and executable. We achieve localization upto 5% and an average localization of 15% in the source code and upto 80% reduction in simulation trace size for a wide variety of bugs in all the important modules of a USB design.