Switch bound allocation for maximizing routability in timing-driven routing of FPGA's

Keyphrases

• Routability 100%
• Timing-driven 100%
• Delay Constraint 50%
• PRESENT Algorithm 25%
• Reduced Delay 25%
• Interconnect Delay 25%
• Channel Routing 25%
• Upper Bound Solution 25%
• Source-to-sink Delay 25%
• Programmable Switches 25%
• Segmented Channel 25%

Computer Science

• Field Programmable Gate Arrays 100%
• Experimental Result 50%
• Bound Approach 50%
• Routing Channel 50%