Surface roughness exacerbated performance degradation in silicon nanowire transistors

D. Basu, M. J. Gilbert, S. K. Banerjee

Research output: Contribution to journalArticlepeer-review


Scaling of silicon devices is fast approaching the limit where a single gate will fail to retain an effective control over the channel region. Of the alternative devices being researched, silicon nanowire transistors (SNWTs) show great promise in terms of scalability, performance, and ease of fabrication. In this work, the authors present the results of self-consistent, three-dimensional fully quantum mechanical simulations of SNWTs to show the role of surface roughness (SR) on the device parameter variation of SNWTs. The authors find additional quantum interference to take place when SR is taken into account in addition to a discrete impurity distribution. Due to this, the variations of the SNWT operational parameters increase about their mean value, indicating a performance concern. However, it is also seen that the quantum interferences are dependent on the dopant locations to a large extent, and for devices with preferential dopant configurations, these effects can be overcome to obtain nearly ballistic behavior.

Original languageEnglish (US)
Pages (from-to)2424-2428
Number of pages5
JournalJournal of Vacuum Science and Technology B: Microelectronics and Nanometer Structures
Issue number5
StatePublished - 2006
Externally publishedYes

ASJC Scopus subject areas

  • Condensed Matter Physics
  • Electrical and Electronic Engineering


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