Supply-noise mitigation techniques in phase-locked loops

Abhijith Arakali, Nema Talebbeydokthi, Srikanth Gondi, Pavan Kumar Hanumolu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Supply-noise significantly affects the jitter performance of ring oscillator-based phase-locked loops (PLLs). While the focus of much of the prior art is on supply-noise in oscillators, this paper illustrates that supply-noise in other building blocks also contribute significantly to PLL output jitter. The current design employs a split-tuned PLL architecture wherein the power supply of the building blocks is derived from the regulated power supply of the VCO. The prototype PLL fabricated in a 0.18/μm digital CMOS process occupies 0.18mm2 and consumes only 3.3mW, from a 1.8V supply, of which 0.54mW is consumed in the regulators, while operating at 1.5GHz. The PLL achieves 33ps and 41ps peak-to-peak jitter with no supply noise and with 100mV peak-to-peak supply noise, respectively.

Original languageEnglish (US)
Title of host publicationESSCIRC 2008 - Proceedings of the 34th European Solid-State Circuits Conference
Pages374-377
Number of pages4
DOIs
StatePublished - Dec 31 2008
Externally publishedYes
Event34th European Solid-State Circuits Conference, ESSCIRC 2008 - Edinburgh, Scotland, United Kingdom
Duration: Sep 15 2008Sep 19 2008

Publication series

NameESSCIRC 2008 - Proceedings of the 34th European Solid-State Circuits Conference

Other

Other34th European Solid-State Circuits Conference, ESSCIRC 2008
Country/TerritoryUnited Kingdom
CityEdinburgh, Scotland
Period9/15/089/19/08

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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