Sub-100 nm gate III-V MOSFET for digital applications

K. Y. Cheng, Milton Feng, Donald Cheng, Chichih Liao

Research output: Chapter in Book/Report/Conference proceedingChapter

Abstract

The performance of nano-CMOS digital ICs is characterized in terms of key figure of merits, which provides a benchmark for III-V compound semiconductor MOSFETs. The selection of III-V channel material is discussed based on the transport properties, i.e., the intrinsic electron mobility and hole mobility, of different III-V alloys. To improve the hole mobility for III-V p-MOSFETs, the effects of strain-induced hole mobility enhancement are reviewed. Critical process issues for self-aligned III-V MOSFET are thermal stability of the oxide-semiconductor interface and source/drain doping limitations. The advantages of self-aligned GaAs enhancement-mode MOSFETs using regrown source and drain regions are demonstrated. Finally, the state-of-the-art device performance of sub-100 nm gate III-V FETs is compared with Si MOSFETs.

Original languageEnglish (US)
Title of host publicationFundamentals of III-V Semiconductor MOSFETs
PublisherSpringer US
Pages285-305
Number of pages21
ISBN (Print)9781441915467
DOIs
StatePublished - Dec 1 2010

ASJC Scopus subject areas

  • Engineering(all)

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  • Cite this

    Cheng, K. Y., Feng, M., Cheng, D., & Liao, C. (2010). Sub-100 nm gate III-V MOSFET for digital applications. In Fundamentals of III-V Semiconductor MOSFETs (pp. 285-305). Springer US. https://doi.org/10.1007/978-1-4419-1547-4_10