TY - GEN
T1 - Study of design factors affecting turn-on time of silicon controlled rectifiers (SCRs) in 90 and 65NM bulk CMOS technologies
AU - Sarro, James Di
AU - Chatty, Kiran
AU - Gauthier, Robert
AU - Rosenbaum, Elyse
PY - 2006
Y1 - 2006
N2 - We explore the effect of layout factors on the turn-on time of Silicon Controlled Rectifiers (SCRs) in 90nm and 65nm bulk CMOS technologies. Using a Very Fast Transmission Line Pulse (VFTLP) tester, we show that a SCR in 65nm bulk CMOS technology can achieve a turn-on time of 500ps with proper design. Using device simulations, we identify factors limiting SCR turn-on time and provide a basis for the presented experimental results.
AB - We explore the effect of layout factors on the turn-on time of Silicon Controlled Rectifiers (SCRs) in 90nm and 65nm bulk CMOS technologies. Using a Very Fast Transmission Line Pulse (VFTLP) tester, we show that a SCR in 65nm bulk CMOS technology can achieve a turn-on time of 500ps with proper design. Using device simulations, we identify factors limiting SCR turn-on time and provide a basis for the presented experimental results.
KW - ESD protection circuits
KW - Electrostatic discharge (ESD)
KW - Silicon Controlled Rectifier (SCR)
UR - http://www.scopus.com/inward/record.url?scp=34250693116&partnerID=8YFLogxK
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U2 - 10.1109/RELPHY.2006.251210
DO - 10.1109/RELPHY.2006.251210
M3 - Conference contribution
AN - SCOPUS:34250693116
SN - 0780394992
SN - 0780394984
SN - 9780780394988
T3 - IEEE International Reliability Physics Symposium Proceedings
SP - 163
EP - 168
BT - 2006 IEEE International Reliability Physics Symposium Proceedings, 44th Annual
T2 - 44th Annual IEEE International Reliability Physics Symposium, IRPS 2006
Y2 - 26 March 2006 through 30 March 2006
ER -