Study of design factors affecting turn-on time of silicon controlled rectifiers (SCRs) in 90 and 65NM bulk CMOS technologies

James Di Sarro, Kiran Chatty, Robert Gauthier, Elyse Rosenbaum

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

We explore the effect of layout factors on the turn-on time of Silicon Controlled Rectifiers (SCRs) in 90nm and 65nm bulk CMOS technologies. Using a Very Fast Transmission Line Pulse (VFTLP) tester, we show that a SCR in 65nm bulk CMOS technology can achieve a turn-on time of 500ps with proper design. Using device simulations, we identify factors limiting SCR turn-on time and provide a basis for the presented experimental results.

Original languageEnglish (US)
Title of host publication2006 IEEE International Reliability Physics Symposium Proceedings, 44th Annual
Pages163-168
Number of pages6
DOIs
StatePublished - 2006
Event44th Annual IEEE International Reliability Physics Symposium, IRPS 2006 - San Jose, CA, United States
Duration: Mar 26 2006Mar 30 2006

Publication series

NameIEEE International Reliability Physics Symposium Proceedings
ISSN (Print)1541-7026

Other

Other44th Annual IEEE International Reliability Physics Symposium, IRPS 2006
Country/TerritoryUnited States
CitySan Jose, CA
Period3/26/063/30/06

Keywords

  • ESD protection circuits
  • Electrostatic discharge (ESD)
  • Silicon Controlled Rectifier (SCR)

ASJC Scopus subject areas

  • General Engineering

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