Study of a CMOS I/O protection circuit using circuit-level simulation

T. Li, D. Suh, S. Ramaswamy, P. Bendix, E. Rosenbaum, A. Kapoor, S. M. Kang

Research output: Contribution to journalConference article


In this work, circuit-level simulation is conducted for a typical two-stage protection circuit. We demonstrate that the circuit failure mechanism is correctly predicted by simulation. Furthermore, the current protection levels estimated by simulation are in good agreement with the experiments; therefore, circuit-level simulation can be used to predict the HBM-ESD protection level. In addition, the failure site is explained by simulation.

Original languageEnglish (US)
Pages (from-to)333-338
Number of pages6
JournalAnnual Proceedings - Reliability Physics (Symposium)
StatePublished - Jan 1 1997
EventProceedings of the 1997 35th Annual IEEE International Reliability Physics Symposium - Denver, CO, USA
Duration: Apr 8 1997Apr 10 1997


ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality

Cite this

Li, T., Suh, D., Ramaswamy, S., Bendix, P., Rosenbaum, E., Kapoor, A., & Kang, S. M. (1997). Study of a CMOS I/O protection circuit using circuit-level simulation. Annual Proceedings - Reliability Physics (Symposium), 333-338.