Stochastic networked computation

Girish Vishnu Varatkar, Sriram Narayanan, Naresh R. Shanbhag, Douglas L. Jones

Research output: Contribution to journalArticlepeer-review

Abstract

In this paper, the stochastic networked computation (SNC) paradigm for designing robust and energy-efficient systems-on-a-chip in nanoscale process technologies, where robust computation is treated as a statistical estimation problem is presented. The benefits of SNC are demonstrated by employing it to design an energy-efficient and robust pseudonoise-code acquisition system for the wireless CDMA2000 standard (http://www.3gpp2.org). Simulations in IBM's 130-nm CMOS process show that the SNC-based architecture enhances the average probability of detection (PDet) in the presence of process variations by two to three orders of magnitude, reduces power by 31%-39%, and reduces the variation in PDet by one to two orders of magnitude at a typical false-alarm rate of 5% over a conventional architecture. SNC performance in the presence of voltage overscaling and across technology nodes (90, 65, 45, and 32 nm) is also studied.

Original languageEnglish (US)
Article number5280185
Pages (from-to)1421-1432
Number of pages12
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume18
Issue number10
DOIs
StatePublished - Oct 1 2010

Keywords

  • Code division multiple access (CDMA)
  • low power
  • nanoscale
  • process variations
  • reliability
  • robust
  • soft errors
  • stochastic

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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