Stochastic networked computation

Girish Vishnu Varatkar; Sriram Narayanan; Naresh R. Shanbhag; Douglas L Jones

doi:10.1109/TVLSI.2009.2024673

Stochastic networked computation

Girish Vishnu Varatkar, Sriram Narayanan, Naresh R. Shanbhag, Douglas L Jones

Research output: Contribution to journal › Article › peer-review

Abstract

In this paper, the stochastic networked computation (SNC) paradigm for designing robust and energy-efficient systems-on-a-chip in nanoscale process technologies, where robust computation is treated as a statistical estimation problem is presented. The benefits of SNC are demonstrated by employing it to design an energy-efficient and robust pseudonoise-code acquisition system for the wireless CDMA2000 standard (http://www.3gpp2.org). Simulations in IBM's 130-nm CMOS process show that the SNC-based architecture enhances the average probability of detection (P_Det) in the presence of process variations by two to three orders of magnitude, reduces power by 31%-39%, and reduces the variation in P_Det by one to two orders of magnitude at a typical false-alarm rate of 5% over a conventional architecture. SNC performance in the presence of voltage overscaling and across technology nodes (90, 65, 45, and 32 nm) is also studied.

Original language	English (US)
Article number	5280185
Pages (from-to)	1421-1432
Number of pages	12
Journal	IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume	18
Issue number	10
DOIs	https://doi.org/10.1109/TVLSI.2009.2024673
State	Published - Oct 2010

Keywords

Code division multiple access (CDMA)
low power
nanoscale
process variations
reliability
robust
soft errors
stochastic

ASJC Scopus subject areas

Software
Hardware and Architecture
Electrical and Electronic Engineering

Online availability

10.1109/TVLSI.2009.2024673

Library availability

Discover UIUC Full Text

Cite this

@article{ef0c390478db4535840837620e56f70b,

title = "Stochastic networked computation",

abstract = "In this paper, the stochastic networked computation (SNC) paradigm for designing robust and energy-efficient systems-on-a-chip in nanoscale process technologies, where robust computation is treated as a statistical estimation problem is presented. The benefits of SNC are demonstrated by employing it to design an energy-efficient and robust pseudonoise-code acquisition system for the wireless CDMA2000 standard (http://www.3gpp2.org). Simulations in IBM's 130-nm CMOS process show that the SNC-based architecture enhances the average probability of detection (PDet) in the presence of process variations by two to three orders of magnitude, reduces power by 31%-39%, and reduces the variation in PDet by one to two orders of magnitude at a typical false-alarm rate of 5% over a conventional architecture. SNC performance in the presence of voltage overscaling and across technology nodes (90, 65, 45, and 32 nm) is also studied.",

keywords = "Code division multiple access (CDMA), low power, nanoscale, process variations, reliability, robust, soft errors, stochastic",

author = "Varatkar, {Girish Vishnu} and Sriram Narayanan and Shanbhag, {Naresh R.} and Jones, {Douglas L}",

note = "Funding Information: Manuscript received January 12, 2009; revised April 23, 2009. First published October 06, 2009; current version published September 24, 2010. This work was supported in part by the Gigascale System Research Center, one of five research centers funded under the Focus Center Research Program, a Semiconductor Research Corporation Program, and by the National Science Foundation under Grant CCF 0729092.",

year = "2010",

month = oct,

doi = "10.1109/TVLSI.2009.2024673",

language = "English (US)",

volume = "18",

pages = "1421--1432",

journal = "IEEE Transactions on Very Large Scale Integration (VLSI) Systems",

issn = "1063-8210",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "10",

}

TY - JOUR

T1 - Stochastic networked computation

AU - Varatkar, Girish Vishnu

AU - Narayanan, Sriram

AU - Shanbhag, Naresh R.

AU - Jones, Douglas L

N1 - Funding Information: Manuscript received January 12, 2009; revised April 23, 2009. First published October 06, 2009; current version published September 24, 2010. This work was supported in part by the Gigascale System Research Center, one of five research centers funded under the Focus Center Research Program, a Semiconductor Research Corporation Program, and by the National Science Foundation under Grant CCF 0729092.

PY - 2010/10

Y1 - 2010/10

N2 - In this paper, the stochastic networked computation (SNC) paradigm for designing robust and energy-efficient systems-on-a-chip in nanoscale process technologies, where robust computation is treated as a statistical estimation problem is presented. The benefits of SNC are demonstrated by employing it to design an energy-efficient and robust pseudonoise-code acquisition system for the wireless CDMA2000 standard (http://www.3gpp2.org). Simulations in IBM's 130-nm CMOS process show that the SNC-based architecture enhances the average probability of detection (PDet) in the presence of process variations by two to three orders of magnitude, reduces power by 31%-39%, and reduces the variation in PDet by one to two orders of magnitude at a typical false-alarm rate of 5% over a conventional architecture. SNC performance in the presence of voltage overscaling and across technology nodes (90, 65, 45, and 32 nm) is also studied.

AB - In this paper, the stochastic networked computation (SNC) paradigm for designing robust and energy-efficient systems-on-a-chip in nanoscale process technologies, where robust computation is treated as a statistical estimation problem is presented. The benefits of SNC are demonstrated by employing it to design an energy-efficient and robust pseudonoise-code acquisition system for the wireless CDMA2000 standard (http://www.3gpp2.org). Simulations in IBM's 130-nm CMOS process show that the SNC-based architecture enhances the average probability of detection (PDet) in the presence of process variations by two to three orders of magnitude, reduces power by 31%-39%, and reduces the variation in PDet by one to two orders of magnitude at a typical false-alarm rate of 5% over a conventional architecture. SNC performance in the presence of voltage overscaling and across technology nodes (90, 65, 45, and 32 nm) is also studied.

KW - Code division multiple access (CDMA)

KW - low power

KW - nanoscale

KW - process variations

KW - reliability

KW - robust

KW - soft errors

KW - stochastic

UR - http://www.scopus.com/inward/record.url?scp=77957588938&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=77957588938&partnerID=8YFLogxK

U2 - 10.1109/TVLSI.2009.2024673

DO - 10.1109/TVLSI.2009.2024673

M3 - Article

AN - SCOPUS:77957588938

SN - 1063-8210

VL - 18

SP - 1421

EP - 1432

JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

IS - 10

M1 - 5280185

ER -

Stochastic networked computation

Abstract

Keywords

ASJC Scopus subject areas

Online availability

Library availability

Related links

Fingerprint

Cite this