TY - GEN
T1 - Still a fight to get it right
T2 - 2017 IEEE International Conference on Rebooting Computing, ICRC 2017
AU - Vasudevan, Shobha
N1 - Publisher Copyright:
©2017 IEEE.
PY - 2017/11/28
Y1 - 2017/11/28
N2 - We live in interesting times. Our systems have unprecedented levels of device integration. Analog and mixed signal components and devices form increasingly large parts of our designs built for low power and high flexibility. New architectures and models of computation that embrace variation like neuromorphic computing are a part of our horizon. Architectures specialized for neural networks and learning algorithms are being built as massive undertakings in contemporary industry as well as with hardware accelerators. Application specific hardware has seen a healthy resurgence for machine learning and vision applications. With all these innovations in architecture and design, how do we know if were getting them right? As designs get more complicated, the"price of the lunch" is paid by verification complexity. We have always aspired to build systems we dont know to check. That problem is going to get much more challenging for systems of the future. What does it mean to verify these massively integrated systems, with new features, new models of computation, non-Traditional architectures and new applications? How do we characterize, define, execute and sign off on the correctness of the most complex systems known to humans? This paper touches upon these questions and presents challenges in these systems of the future.
AB - We live in interesting times. Our systems have unprecedented levels of device integration. Analog and mixed signal components and devices form increasingly large parts of our designs built for low power and high flexibility. New architectures and models of computation that embrace variation like neuromorphic computing are a part of our horizon. Architectures specialized for neural networks and learning algorithms are being built as massive undertakings in contemporary industry as well as with hardware accelerators. Application specific hardware has seen a healthy resurgence for machine learning and vision applications. With all these innovations in architecture and design, how do we know if were getting them right? As designs get more complicated, the"price of the lunch" is paid by verification complexity. We have always aspired to build systems we dont know to check. That problem is going to get much more challenging for systems of the future. What does it mean to verify these massively integrated systems, with new features, new models of computation, non-Traditional architectures and new applications? How do we characterize, define, execute and sign off on the correctness of the most complex systems known to humans? This paper touches upon these questions and presents challenges in these systems of the future.
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U2 - 10.1109/ICRC.2017.8123645
DO - 10.1109/ICRC.2017.8123645
M3 - Conference contribution
AN - SCOPUS:85043481611
T3 - 2017 IEEE International Conference on Rebooting Computing, ICRC 2017 - Proceedings
SP - 1
EP - 8
BT - 2017 IEEE International Conference on Rebooting Computing, ICRC 2017 - Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 8 November 2017 through 9 November 2017
ER -