Sthira: A Formal Approach to Minimize Voltage Guardbands under Variation in Networks-on-Chip for Energy Efficiency

Raghavendra Pradyumna Pothukuchi, Amin Ansari, Bhargava Gopireddy, Josep Torrellas

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Networks-on-Chip (NoCs) in chip multiprocessors are prone to within-die process variation as they span the whole chip. To tolerate variation, their voltages (Vdd) carry over-provisioned guardbands. As a result, prior work has proposed to save energy by operating at reduced Vdd while occasionally suffering and fixing errors. Unfortunately, these proposals use heuristic controller designs that provide no error bounds guarantees.In this work, we develop a scheme that dynamically minimizes the Vdd of groups of routers in a variation-prone NoC using formal control-theoretic methods. The scheme, called Sthira, saves substantial energy while guaranteeing the stability and convergence of error rates. We also enhance the scheme with a low-cost secondary network that retransmits erroneous packets for higher energy efficiency. The enhanced scheme is called Sthira+. We evaluate Sthira and Sthira+ with simulations of NoCs with 64-100 routers. In an NoC with 8 routers per Vdd domain, our schemes reduce the average energy consumptionof the NoC by 27%; in a futuristic NoC with one router per Vdd domain, Sthira+ and Sthira reduce the average energy consumption by 36% and 32%, respectively. The performance impact is negligible. These are significant savings over the state-of-the-art. We conclude that formal control is essential, and that the cheaper Sthira is more cost-effective than Sthira+.

Original languageEnglish (US)
Title of host publicationProceedings - 26th International Conference on Parallel Architectures and Compilation Techniques, PACT 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages260-272
Number of pages13
ISBN (Electronic)9781467395243
DOIs
StatePublished - Oct 31 2017
Event26th International Conference on Parallel Architectures and Compilation Techniques, PACT 2017 - Portland, United States
Duration: Sep 9 2017Sep 13 2017

Publication series

NameParallel Architectures and Compilation Techniques - Conference Proceedings, PACT
Volume2017-September
ISSN (Print)1089-795X

Other

Other26th International Conference on Parallel Architectures and Compilation Techniques, PACT 2017
CountryUnited States
CityPortland
Period9/9/179/13/17

Keywords

  • Control theory
  • Network on chip
  • Variation

ASJC Scopus subject areas

  • Software
  • Theoretical Computer Science
  • Hardware and Architecture

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    Pothukuchi, R. P., Ansari, A., Gopireddy, B., & Torrellas, J. (2017). Sthira: A Formal Approach to Minimize Voltage Guardbands under Variation in Networks-on-Chip for Energy Efficiency. In Proceedings - 26th International Conference on Parallel Architectures and Compilation Techniques, PACT 2017 (pp. 260-272). (Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT; Vol. 2017-September). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/PACT.2017.23