Analog to digital conversion is often a critical component of a digital communication link. However, the designs of typical architectures for analog to digital converters (ADCs) are focused primarily on signal reconstruction rather than gathering information for the reliable detection of symbols sent through a channel. Therefore, we consider new architectures for statistics gathering converters (SGCs), and demonstrate that these architectures achieve good communication performance while removing the artificial constraints imposed by the typical ADC design metrics. In this paper, we extend previous work on system level metrics for statistics gathering converters (SGCs). For the particular case of the delay-line based SGC, we demonstrate two important facts. First, we consider the comparison between the performance indicated by system level metrics (BER and LMMSE) with the results of a simulated communication scenario utilizing a low complexity least mean squares equalizer. Simulations demonstrate that the system level metrics are an accurate representation of the realizable communication performance of a system using the converter in question, and that such performance can be nearly achieved by the delay-line SGC using a specially designed low complexity (LMS) equalizer that takes into account the particular structure of the SGC. Second, we demonstrate that the communication performance of the delay-line SGC is robust to significant levels of process variation, which manifest in random realizations of the values of the various SGC circuit elements. Notably, this is contrary to the strict requirements on process variation imposed by traditional metrics (SNDR, SFDR, THD) on conventional analog to digital converter designs.