Statistical Learning of IC Models for System-Level ESD Simulation

Jie Xiong, Zaichen Chen, Maxim Raginsky, Elyse Rosenbaum

Research output: Contribution to journalArticlepeer-review

Abstract

To enable accurate system-level electrostatic discharge (ESD) simulation, this article applies statistical learning to obtain I/O port models of the victim integrated circuits (ICs). A quasi-static I-V model derived using kernel regression can capture the circuit board dependency of the behavior observed at the I/O pin, regardless if there is snapback. The non-parametric kernel model can be reduced to a system-specific parametric model, which has smaller requirements for computing time and memory. In some cases, transient system-level ESD simulation may require the IC model to replicate the dynamic behavior of the nonlinear circuit. A recurrent neural network is demonstrated to be a suitable model in such cases. This article provides a detailed RNN training flow for IC pin modeling, and presents a Verilog-A implementation of the RNN for use with Simulation Program with Integrated Circuit Emphasis (SPICE)-type simulators.

Original languageEnglish (US)
Pages (from-to)1302-1311
Number of pages10
JournalIEEE Transactions on Electromagnetic Compatibility
Volume63
Issue number5
DOIs
StatePublished - Oct 1 2021
Externally publishedYes

Keywords

  • Electrostatic discharge (ESD)
  • integrated circuit (IC) modeling
  • kernel regression
  • recurrent neural network (RNN)

ASJC Scopus subject areas

  • Atomic and Molecular Physics, and Optics
  • Condensed Matter Physics
  • Electrical and Electronic Engineering

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