Abstract
Emerging data-intensive applications with frequent small random read operations challenge the throughput capabilities of conventional SSD architectures. Although Compute Express Link enabled SSDs allow for fine-grained data access with reduced latency, their read throughput remains limited by legacy block-oriented designs. To address this, we propose srNAND, an advanced NAND flash architecture for CXL SSDs. It uses a two-stage ECC decoding mechanism to reduce read amplification, an optimized read command sequence to boost parallelism, and a request merging module to eliminate redundant operations. Our evaluation shows that srSSD can improve read throughput by up to 10.4× compared to conventional CXL SSDs.
| Original language | English (US) |
|---|---|
| Pages (from-to) | 197-200 |
| Number of pages | 4 |
| Journal | IEEE Computer Architecture Letters |
| Volume | 24 |
| Issue number | 2 |
| DOIs | |
| State | Published - 2025 |
Keywords
- CXL.mem
- Compute Express Link
- NAND flash architecture
- NAND flash memory
- SSD
- flash read sequence
- partial flash read
ASJC Scopus subject areas
- Hardware and Architecture