Spin-Based Reconfigurable Logic for Power- And Area-Efficient Applications

Nikhil Rangarajan; Satwik Patnaik; Johann Knechtel; Ozgur Sinanoglu; Shaloo Rakheja

doi:10.1109/MDAT.2019.2895021

Spin-Based Reconfigurable Logic for Power- And Area-Efficient Applications

Nikhil Rangarajan
, Satwik Patnaik
, Johann Knechtel
, Ozgur Sinanoglu
, Shaloo Rakheja

Research output: Contribution to journal › Article › peer-review

Abstract

Editor's note: This article proposes a reconfigurable logic family comprised of spin-based devices that may be dynamically configured/reconfigured owing the versatility of the giant spin-Hall effect (GSHE) device. A GSHE device can be used to realize numerous Boolean logic functions, and the proposed spin-based polymorphic logic has the potential to be extremely area efficient. - Michael Niemier, University of Notre Dame.

Original language	English (US)
Article number	8625518
Pages (from-to)	22-30
Number of pages	9
Journal	IEEE Design and Test
Volume	36
Issue number	3
DOIs	https://doi.org/10.1109/MDAT.2019.2895021
State	Published - Jun 2019
Externally published	Yes

Keywords

FPGA
Reconfigurable computing
giant spin-Hall effect
polymorphic gates
spin-domain

ASJC Scopus subject areas

Software
Hardware and Architecture
Electrical and Electronic Engineering

Online availability

10.1109/MDAT.2019.2895021

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note = "N. Rangarajan and S. Patnaik contributed equally to this article. This work was supported in part by the Semiconductor Research Corporation (SRC), in part by National Science Foundation (NSF) under Grant ECCS 1740136, and in part by the MRSEC Program of the National Science Foundation under Award DMR-1420073.",

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AU - Knechtel, Johann

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AU - Rakheja, Shaloo

N1 - N. Rangarajan and S. Patnaik contributed equally to this article. This work was supported in part by the Semiconductor Research Corporation (SRC), in part by National Science Foundation (NSF) under Grant ECCS 1740136, and in part by the MRSEC Program of the National Science Foundation under Award DMR-1420073.

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Spin-Based Reconfigurable Logic for Power- And Area-Efficient Applications

Abstract

Keywords

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