SPARK: A Scalable Partitioning and Routing Framework for Multi-FPGA Systems

Xinshi Zang, Evangeline F.Y. Young, Martin D.F. Wong

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

With the size of modern VLSI circuits growing in size to billions of transistors, multi-FPGA systems have been widely applied in circuit emulation and prototyping. To make full advantage of limited FPGA resources and improve the system frequency, designing a flexible multi-FPGA system with a corresponding design compilation flow is an important research problem in both industry and academia. In this work, we propose a practical and scalable partitioning and routing framework, named SPARK, for a multi-FPGA system with an adjustable near-square mesh shape and the minimum number of FPGAs. To resolve the significant constraints on multiple hardware resources for partitioning, SPARK leverages the general hypergraph partitioning tool by combining it with an efficient legalization algorithm to minimize cut size without resource overflow. We also propose novel max_cut-driven maze routing and max_hop-driven refinement algorithms to optimize the max_cut and max_hop in multi-FPGA systems meanwhile and improve the system frequency. Extensive experiments using the largest public circuit benchmarks for FPGA and several small FPGA settings from the industry demonstrate the effectiveness and efficiency of SPARK.

Original languageEnglish (US)
Title of host publicationGLSVLSI 2023 - Proceedings of the Great Lakes Symposium on VLSI 2023
PublisherAssociation for Computing Machinery
Pages593-598
Number of pages6
ISBN (Electronic)9798400701252
DOIs
StatePublished - Jun 5 2023
Externally publishedYes
Event33rd Great Lakes Symposium on VLSI, GLSVLSI 2023 - Knoxville, United States
Duration: Jun 5 2023Jun 7 2023

Publication series

NameProceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Conference

Conference33rd Great Lakes Symposium on VLSI, GLSVLSI 2023
Country/TerritoryUnited States
CityKnoxville
Period6/5/236/7/23

Keywords

  • multi-fpga systems
  • partitioning
  • routing

ASJC Scopus subject areas

  • General Engineering

Fingerprint

Dive into the research topics of 'SPARK: A Scalable Partitioning and Routing Framework for Multi-FPGA Systems'. Together they form a unique fingerprint.

Cite this