Software upset analysis: A case study of the HS1602 microprocessor

G. S. Choi, R. K. Iyer

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper describes a simulation based approach to quantify the impact of low-level transient errors at the software execution level. Automated analysis, for the run-time injection of transients at the device level and the assessment of the resulting impact on the program-control flow, is described. Using test workloads, the type of upsets at the program-flow level which can result from fault injection are determined. The methodology is illustrated by a case study of a microprocessor, used in the jet-engine controller of Boeing 747 and 757 aircrafts. For each section in the test program, the chance of having single and multiple upsets from the fault injection is determined. The analysis showed that about 20% of all upsets are multiple in nature. The result suggests that current methods of validation that assume single upsets may be inadequate.

Original languageEnglish (US)
Title of host publicationATS 1993 Proceedings - 2nd Asian Test Symposium
PublisherIEEE Computer Society
Pages49-54
Number of pages6
ISBN (Electronic)081863930X
DOIs
StatePublished - Jan 1 1993
Event2nd IEEE Asian Test Symposium, ATS 1993 - Beijing, China
Duration: Nov 16 1993Nov 18 1993

Publication series

NameProceedings of the Asian Test Symposium
ISSN (Print)1081-7735

Conference

Conference2nd IEEE Asian Test Symposium, ATS 1993
CountryChina
CityBeijing
Period11/16/9311/18/93

Keywords

  • Design for dependability
  • Fault injection
  • Single and multiple upsets
  • Statistical analysis
  • VLSI simulation

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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